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Publications of Author

1. Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee
   A flexible data-interlacing architecture for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP]
   ASAP, 1997, pp:96-0 [Conf]
   
2. Yeong-Kang Lai, Lien-Fei Chen
   A high data-reuse architecture with double-slice processing for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:716-719 [Conf]
   
3. Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung
   A simple and cost effective video encoder with memory-reducing CAVLC. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:432-435 [Conf]
   
4. Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu
   A two-way SIMD-based reconfigurable computing architecture for multimedia applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4578-4581 [Conf]
   
5. Yeong-Kang Lai, Li-Chung Chang, Lien-Fei Chen, Chi-Chung Chou, Chun-Wei Chiu
   A novel memoryless AES cipher architecture for networking applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2004, pp:333-336 [Conf]
   
6. Yeong-Kang Lai, Han-Jen Hsu
   A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:492-495 [Conf]
   
7. Yeong-Kang Lai, Yu-Chuan Shu
   VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:57-60 [Conf]
   
8. Yeong-Kang Lai, Lien-Fei Chen
   A performance-driven configurable motion estimator for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:233-236 [Conf]
   
9. Lien-Fei Chen, Yeong-Kang Lai
   VLSI architecture of the reconfigurable computing engine for digital signal processing applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:937-940 [Conf]
   
10. 
    Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm. [Citation Graph (, )][DBLP]
    
    
11. 
    Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder. [Citation Graph (, )][DBLP]
    
    
12. 
    A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. [Citation Graph (, )][DBLP]
    
    
13. 
    Model-based early termination scheme for H.264/AVC inter prediction. [Citation Graph (, )][DBLP]