The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Liang-Gee Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee
    A flexible data-interlacing architecture for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:96-0 [Conf]
  2. Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
    Hardware architecture design of an H.264/AVC video codec. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:750-757 [Conf]
  3. Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao
    A hardware-oriented design for weighted median filters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku
    A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:145-150 [Conf]
  5. Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang
    Design and implementation of JPEG encoder IP core. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:29-30 [Conf]
  6. Liang-Gee Chen
    Dances with multimedia: embedded video codec design. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:1- [Conf]
  7. Chung-Jr Lian, Yu-Wen Huang, Hung-Chi Fang, Yung-Chi Chang, Liang-Gee Chen
    PEG, MPEG-4, and H.264 Codec IP Development. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1118-1119 [Conf]
  8. Thou-Ho Chen, Liang-Gee Chen, Yi-Shing Chang
    Design of Concurrent Error-Detectable VLSI-Based Array Dividers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:72-75 [Conf]
  9. Liang-Gee Chen, Wai-Ting Chen, Yen-Shen Jehng, Tzi-Dar Chiueh
    A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:617-620 [Conf]
  10. Pinhong Chen, Jyuo-Min Shyu, Liang-Gee Chen
    Hardware Verification Using Symbolic State Transition Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:54-57 [Conf]
  11. Yu-Lin Chang, Ching-Yeh Chen, Shyh-Feng Lin, Liang-Gee Chen
    Motion compensated de-interlacing with adaptive global motion estimation and compensation. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:693-696 [Conf]
  12. Te-Hao Chang, Li-Lin Chen, Chung-Jr Lian, Hong-Hui Chen, Liang-Gee Chen
    Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2002, pp:85-88 [Conf]
  13. Jing-Kng Chang, Hung-Chi Fang, Yen-Wei Huang, Liang-Gee Chen
    Architecture of MPEG-7 color structure description generator for realtime video applications. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:2813-2816 [Conf]
  14. Wei-Min Chao, Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
    Platform architecture design for MEG-4 video coding. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:93-96 [Conf]
  15. Mei-Juan Chen, Liang-Gee Chen, Ruei-Xi Chen
    Error Resilience for Block Loss with Overlapped Motion Compensation. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1997, pp:105-0 [Conf]
  16. Shao-Yi Chien, Ching-Yeh Chen, Wei-Min Chao, Chih-Wei Hsu, Yu-Wen Huang, Liang-Gee Chen
    A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 2002, pp:193-196 [Conf]
  17. Shao-Yi Chien, Shu-Han Yu, Li-Fu Ding, Yun-Nien Huang, Liang-Gee Chen
    Efficient stereo video coding system for immersive teleconference with two-stage hybrid disparity estimation algorithm. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 2003, pp:749-752 [Conf]
  18. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2003, pp:571-574 [Conf]
  19. Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hua Chen, Chung-Jr Lian, Liang-Gee Chen
    System analysis of VLSI architecture for motion-compensated temporal filtering. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:992-995 [Conf]
  20. Yung-Chi Chang, Chao-Chih Huang, Hao-Chieh Chang, Hung-Chi Fang, Liang-Gee Chen
    Error-Propagation Analysis and Concealment Strategy for MPEG-4 Video Bitstream with Data Partitioning. [Citation Graph (0, 0)][DBLP]
    ICME, 2001, pp:- [Conf]
  21. Liang-Gee Chen, Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen
    Analysis and Architecture Design of JPEG2000. [Citation Graph (0, 0)][DBLP]
    ICME, 2001, pp:- [Conf]
  22. Shao-Yi Chien, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
    Automatic Video Segmentation For MPEG-4 Using Predictivewatershed. [Citation Graph (0, 0)][DBLP]
    ICME, 2001, pp:- [Conf]
  23. Te-Hao Chang, Chung-Jr Lian, Hong-Hui Chen, Jing-Ying Chang, Liang-Gee Chen
    Effective hardware-oriented technique for the rate control of JPEG2000 encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:684-687 [Conf]
  24. Wei-Min Chao, Tung-Chien Chen, Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
    Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:788-791 [Conf]
  25. Yi-Hau Chen, Ching-Yeh Chen, Liang-Gee Chen
    Architecture of global motion compensation for MPEG-4 advanced simple profile. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:1798-1801 [Conf]
  26. To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
    Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2931-2934 [Conf]
  27. Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen
    Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1790-1793 [Conf]
  28. Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
    Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5190-5193 [Conf]
  29. Shao-Yi Chien, Ching-Yeh Chen, Wei-Min Chao, Yu-Wen Huang, Liang-Gee Chen
    Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:720-723 [Conf]
  30. Li-Fu Ding, Shao-Yi Chien, Yu-Wen Huang, Yu-Lin Chang, Liang-Gee Chen
    Stereo video coding system with hybrid coding based on joint prediction scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6082-6085 [Conf]
  31. Hung-Chi Fang, Tu-Chih Wang, Chung-Jr Lian, Te-Hao Chang, Liang-Gee Chen
    High speed memory efficient EBCOT architecture for JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:736-739 [Conf]
  32. Jue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen
    Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1567-1570 [Conf]
  33. Jue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen
    High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:85-88 [Conf]
  34. Chih-Wei Hsu, Yung-Chi Chang, Wei-Min Chao, Liang-Gee Chen
    Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:784-787 [Conf]
  35. Sheng-Chieh Huang, Liang-Gee Chen, Thou-Ho Chen
    The Chip Design of A 32-b Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:167-170 [Conf]
  36. Yu-Wen Huang, Chia-Lin Lee, Ching-Yeh Chen, Liang-Gee Chen
    One-pass computation-aware motion estimation with adaptive search strategy. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5469-5472 [Conf]
  37. Yu-Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, Liang-Gee Chen
    Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:796-799 [Conf]
  38. Her-Ming Jong, Liang-Gee Chen, Tzi-Dar Chiueh
    Parallel Architectures of 3-Step Search Block-Matching Algorithm for Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:209-212 [Conf]
  39. Chung-Wei Ku, Liang-Gee Chen, Tzi-Dar Chiueh, Her-Ming Jong
    Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:139-142 [Conf]
  40. Shyh-Feng Lin, Yu-Lin Chang, Liang-Gee Chen
    Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:696-699 [Conf]
  41. Tsung-Han Tsai, Shih-Way Huang, Liang-Gee Chen
    Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:552-555 [Conf]
  42. Tu-Chih Wang, Yu-Wen Huang, Hung-Chi Fang, Liang-Gee Chen
    Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:800-803 [Conf]
  43. Hao-Chieh Chang, Zhong-Lan Yang, Chung-Jr Lian, Liang-Gee Chen
    Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:193-196 [Conf]
  44. Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen, Liang-Gee Chen
    Lifting based discrete wavelet transform architecture for JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:445-448 [Conf]
  45. Mei-Yun Hsu, Hao-Chieh Chang, Yi-Chu Wang, Liang-Gee Chen
    Scalable module-based architecture for MPEG-4 BMA motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:245-248 [Conf]
  46. Kuan-Fu Chen, Chung-Jr Lian, Hong-Hui Chen, Liang-Gee Chen
    Analysis and architecture design of EBCOT for JPEG-2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:765-768 [Conf]
  47. Shao-Yi Chien, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
    A hybrid morphology processing units architecture for real-time video segmentation systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:275-278 [Conf]
  48. Tsung-Han Tsai, Liang-Gee Chen
    A cost effective architecture design of inverse quantization and multichannel processing for MPEG-2 audio decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:548-551 [Conf]
  49. Hao-Chieh Chang, Liang-Gee Chen, Yung-Chi Chang, Sheng-Chieh Huang
    A VLSI architecture design of VLC encoder for high data rate video/image coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:398-401 [Conf]
  50. Sheng-Chieh Huang, Liang-Gee Chen, Hao-Chieh Chang
    A novel image compression algorithm by using Log-Exp transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:17-20 [Conf]
  51. Jun-Fu Shen, Liang-Gee Chen, Hao-Chieh Chang, Tu-Chih Wang
    Low power full-search block-matching motion estimation chip for H.263+. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:299-302 [Conf]
  52. Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
    Hardware architecture design for H.264/AVC intra frame coder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:269-272 [Conf]
  53. Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
    Reconfigurable discrete cosine transform processor for object-based video signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:353-356 [Conf]
  54. Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen
    Low-power parallel tree architecture for full search block-matching motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:313-316 [Conf]
  55. Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen
    Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:273-276 [Conf]
  56. Ching-Yeh Chen, Shao-Yi Chien, Wei-Min Chao, Yu-Wen Huang, Liang-Gee Chen
    Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:301-304 [Conf]
  57. Yu-Lin Chang, Shyh-Feng Lin, Liang-Gee Chen
    Extended intelligent edge-based line average with its implementation and test method. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:341-344 [Conf]
  58. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    B-spline factorization-based architecture for inverse discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:829-832 [Conf]
  59. Hong-Hui Chen, Chung-Jr Lian, Te-Hao Chang, Liang-Gee Chen
    Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:329-332 [Conf]
  60. Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen
    A hardware accelerator for video segmentation using programmable morphology PE array. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:341-344 [Conf]
  61. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:565-568 [Conf]
  62. Chia-Ho Pan, I-Hsien Lee, Sheng-Chieh Huang, Chih-Chi Cheng, Chung-Jr Lian, Liang-Gee Chen
    Application Layer Error Correction Scheme for Video Header Protection on Wireless Network. [Citation Graph (0, 0)][DBLP]
    ISM, 2005, pp:499-505 [Conf]
  63. Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
    MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:172-175 [Conf]
  64. Jing-Ying Chang, Chung-Jr Lian, Hung-Chi Fang, Liang-Gee Chen
    Architecture and Analysis of Color Structure Descriptor for Real-Time Video Indexing and Retrieval. [Citation Graph (0, 0)][DBLP]
    PCM (2), 2004, pp:130-137 [Conf]
  65. Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
    Reconfigurable Platform for Content Science Research. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:481-486 [Conf]
  66. Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
    Efficient video segmentation algorithm for real-time MPEG-4 camera system. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:1087-1098 [Conf]
  67. Shao-Yi Chien, Shu-Han Yu, Li-Fu Ding, Yun-Nien Huang, Liang-Gee Chen
    Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach. [Citation Graph (0, 0)][DBLP]
    VCIP, 2003, pp:1521-1530 [Conf]
  68. Bing-Yu Hsieh, Yu-Wen Huang, Tu-Chih Wang, Shao-Yi Chien, Liang-Gee Chen
    Fast motion estimation algorithm for H.264/MPEG-4 AVC by using multiple reference frame skipping criteria. [Citation Graph (0, 0)][DBLP]
    VCIP, 2003, pp:1551-1560 [Conf]
  69. Yu-Wen Huang, Shao-Yi Chien, Bing-Yu Hsieh, Liang-Gee Chen
    Automatic threshold decision of background registration technique for video segmentation. [Citation Graph (0, 0)][DBLP]
    VCIP, 2002, pp:552-563 [Conf]
  70. Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
    VLSI implementation of shape-adaptive discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    VCIP, 2002, pp:655-666 [Conf]
  71. Yi-Chu Wang, Hao-Chieh Chang, Wei-Ming Chao, Liang-Gee Chen
    Efficient architecture of binary motion estimation for MPEG-4 shape coding. [Citation Graph (0, 0)][DBLP]
    VCIP, 2001, pp:959-967 [Conf]
  72. Lih-Gwo Jeng, Liang-Gee Chen
    Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:148-153 [Conf]
  73. Hao-Chieh Chang, Yung-Chi Chang, Yi-Chu Wang, Wei-Ming Chao, Liang-Gee Chen
    VLSI architecture design of MPEG-4 shape coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:9, pp:741-0 [Journal]
  74. Yu-Lin Chang, Shyh-Feng Lin, Ching-Yeh Chen, Liang-Gee Chen
    Video de-interlacing by adaptive 4-field global/local motion compensated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:12, pp:1569-1582 [Journal]
  75. Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Liang-Gee Chen
    Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:6, pp:673-688 [Journal]
  76. Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Liang-Gee Chen
    Level C+ data reuse scheme for motion estimation with corresponding coding orders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:4, pp:553-558 [Journal]
  77. Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen
    Predictive watershed: a fast watershed algorithm for video segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:5, pp:453-461 [Journal]
  78. Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
    Efficient moving object segmentation algorithm using background registration technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:7, pp:577-586 [Journal]
  79. Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
    Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:9, pp:1156-1169 [Journal]
  80. Hung-Chi Fang, Yu-Wei Chang, Tu-Chih Wang, Chung-Jr Lian, Liang-Gee Chen
    Parallel embedded block coding architecture for JPEG 2000. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:9, pp:1086-1097 [Journal]
  81. Yu-Wen Huang, Shyh-Yih Ma, Chun-Fu Shen, Liang-Gee Chen
    Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:1, pp:111-117 [Journal]
  82. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:7, pp:910-920 [Journal]
  83. Yu-Wen Huang, Shao-Yi Chien, Bing-Yu Hsieh, Liang-Gee Chen
    Global elimination algorithm and architecture design for fast block matching motion estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2004, v:14, n:6, pp:898-907 [Journal]
  84. Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
    Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:378-401 [Journal]
  85. Yu-Wen Huang, Bing-Yu Hsieh, Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
    Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:4, pp:507-522 [Journal]
  86. Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen, Liang-Gee Chen
    Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:3, pp:219-230 [Journal]
  87. Po-Cheng Wu, Liang-Gee Chen
    An efficient architecture for two-dimensional discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:4, pp:536-545 [Journal]
  88. Jun-Fu Shen, Tu-Chih Wang, Liang-Gee Chen
    A novel low-power full-search block-matching motion-estimation design for H.263+. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:7, pp:890-897 [Journal]
  89. Tu-Chih Wang, Hung-Chi Fang, Liang-Gee Chen
    Low-delay and error-robust wireless video transmission for video communications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:12, pp:1049-0 [Journal]
  90. Shao-Yi Chien, Yu-Wen Huang, Bing-Yu Hsieh, Shyh-Yih Ma, Liang-Gee Chen
    Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2004, v:6, n:5, pp:732-748 [Journal]
  91. Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen
    System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1001-1004 [Conf]
  92. Chun-Chia Chen, Yu-Wei Chang, Hung-Chi Fang, Liang-Gee Chen
    Analysis of scalable architecture for the embedded block coding in JPEG 2000. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  93. Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen
    Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  94. Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang-Gee Chen
    Frame-level data reuse for motion-compensated temporal filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  95. You-Ming Tsao, Chi-Ling Wu, Shao-Yi Chien, Liang-Gee Chen
    Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  96. Chih-Chi Cheng, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen
    Analysis and VLSI architecture of update step in motion-compensated temporal filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  97. Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
    Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  98. Chi-Sun Tang, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen
    Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  99. Tung-Chien Chen, Chuan-Yung Tsai, Yu-Wen Huang, Liang-Gee Chen
    Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2007, v:17, n:2, pp:242-247 [Journal]
  100. Lih-Gwo Jeng, Liang-Gee Chen
    Rate-optimal DSP synthesis by pipeline and minimum unfolding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:81-88 [Journal]
  101. Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
    Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:3, pp:241-255 [Journal]
  102. Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen
    Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:3, pp:297-320 [Journal]
  103. Yung-Chi Chang, Wei-Min Chao, Chih-Wei Hsu, Liang-Gee Chen
    Platform-Based MPEG-4 SOC Design for Video Communications. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:1, pp:7-19 [Journal]
  104. Yung-Chi Chang, Chih-Wei Hsu, Wei-Min Chao, Liang-Gee Chen
    Interactive Content-aware Video Streaming System with Fine Granularity Scalability. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:1-2, pp:117-134 [Journal]

  105. A Localized Approach to Abandoned Luggage Detection with Foreground-Mask Sampling. [Citation Graph (, )][DBLP]


  106. Hardware-efficient belief propagation. [Citation Graph (, )][DBLP]


  107. iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. [Citation Graph (, )][DBLP]


  108. A real-time augmented view synthesis system for transparent car pillars. [Citation Graph (, )][DBLP]


  109. A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design. [Citation Graph (, )][DBLP]


  110. Relative Depth Layer Extraction for Monoscopic Video by Use of Multidimensional Filter. [Citation Graph (, )][DBLP]


  111. Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System. [Citation Graph (, )][DBLP]


  112. Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME. [Citation Graph (, )][DBLP]


  113. Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. [Citation Graph (, )][DBLP]


  114. Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications. [Citation Graph (, )][DBLP]


  115. Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder. [Citation Graph (, )][DBLP]


  116. Efficient Depth Image Based Rendering with Edge Dependent Depth Filter and Interpolation. [Citation Graph (, )][DBLP]


  117. Depth Map Generation for 2D-to-3D Conversion by Short-Term Motion Assisted Color Segmentation. [Citation Graph (, )][DBLP]


  118. 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. [Citation Graph (, )][DBLP]


  119. Architecture design of high performance embedded compression for high definition video coding. [Citation Graph (, )][DBLP]


  120. Scalable video adaptation optimization using soft decision scheme. [Citation Graph (, )][DBLP]


  121. Multiview video hybrid coding system with texture-depth synthesis. [Citation Graph (, )][DBLP]


  122. Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding. [Citation Graph (, )][DBLP]


  123. Algorithm and architecture for object tracking using particle filter. [Citation Graph (, )][DBLP]


  124. Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors. [Citation Graph (, )][DBLP]


  125. Frame-parallel design strategy for high definition B-frame H.264/AVC encoder. [Citation Graph (, )][DBLP]


  126. Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems. [Citation Graph (, )][DBLP]


  127. A cost effective reconfigurable memory for multimedia multithreading streaming architecture. [Citation Graph (, )][DBLP]


  128. Intelligent Content-Aware Model-Free Low Power Evoked Neural Signal Compression. [Citation Graph (, )][DBLP]


  129. Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. [Citation Graph (, )][DBLP]


  130. Error recovery for MPEG-4 shape and texture information. [Citation Graph (, )][DBLP]


  131. Real-time deblocking filter for MPEG-4 systems. [Citation Graph (, )][DBLP]


  132. Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. [Citation Graph (, )][DBLP]


  133. Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension. [Citation Graph (, )][DBLP]


  134. Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition. [Citation Graph (, )][DBLP]


  135. Analysis of belief propagation for hardware realization. [Citation Graph (, )][DBLP]


  136. Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture. [Citation Graph (, )][DBLP]


  137. Fast motion estimation with inter-view motion vector prediction for stereo and multiview video coding. [Citation Graph (, )][DBLP]


  138. Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC. [Citation Graph (, )][DBLP]


  139. Fast belief propagation process element for high-quality stereo estimation. [Citation Graph (, )][DBLP]


  140. Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control. [Citation Graph (, )][DBLP]


  141. Cache-based integer motion/disparity estimation for quad-HD H.264/AVC and HD multiview video coding. [Citation Graph (, )][DBLP]


Search in 0.064secs, Finished in 0.075secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002