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Patrick Schaumont: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:15-18 [Conf]
  2. Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
    Virtual Java/FPGA interface for networked reconfiguration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:558-563 [Conf]
  3. David Hwang, Bo-Cheng Lai, Patrick Schaumont, Ingrid Verbauwhede
    A Security Protocol for Biometric Smart Cards. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2002, pp:- [Conf]
  4. Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
    Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:303-311 [Conf]
  5. Ingrid Verbauwhede, Patrick Schaumont
    The happy marriage of architecture and application in next-generation reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:363-376 [Conf]
  6. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:354-365 [Conf]
  7. Eric Simpson, Patrick Schaumont
    Offline Hardware/Software Authentication for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:311-323 [Conf]
  8. Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Ivo Bolsens
    Hardware/software partitioning of embedded system in OCAPI-xl. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:30-35 [Conf]
  9. Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    Microcoded coprocessor for embedded secure biometric authentication systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:130-135 [Conf]
  10. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  11. David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede
    Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:60-65 [Conf]
  12. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels
    A 10 Mbit/s Upstream Cable Modem with Automatic equalization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:337-340 [Conf]
  13. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens
    Hardware Reuse at the Behavioral Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:784-789 [Conf]
  14. Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
    Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:634-639 [Conf]
  15. Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede
    Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:27-30 [Conf]
  16. Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
    A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:172-177 [Conf]
  17. Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
    A Programming Environment for the Design of Complex High Speed ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:315-320 [Conf]
  18. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:222-227 [Conf]
  19. Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens
    A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:271-0 [Conf]
  20. Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee
    Standards for System-Level Design: Practical Reality or Solution in Search of a Question? [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:576-0 [Conf]
  21. Robert Pasko, Serge Vernalde, Patrick Schaumont
    Techniques to Evolve a C++ Based System Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:302-309 [Conf]
  22. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Design with race-free hardware semantics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:571-576 [Conf]
  23. Patrick Schaumont, Ingrid Verbauwhede
    Interactive Cosimulation with Partial Evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:642-647 [Conf]
  24. Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
    Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:988-995 [Conf]
  25. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:804-805 [Conf]
  26. Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede
    Process Isolation for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:164-170 [Conf]
  27. Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
    Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:264-274 [Conf]
  28. Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
    Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:102-104 [Conf]
  29. Doris Ching, Patrick Schaumont, Ingrid Verbauwhede
    Integrated Modeling and Generation of a Reconfigurable Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  30. Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede
    Embedded Software Integration for Coarse-Grain Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  31. Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla
    Interoperability as a design issue in C++ based modeling environments. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:87-92 [Conf]
  32. Robert Pasko, Patrick Schaumont, Veerle Derudder, Daniela Durackova
    Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:100-106 [Conf]
  33. Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
    Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:72-77 [Conf]
  34. Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede
    Architectural Design Features of a Programmable High Throughput AES Coprocessor. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:498-502 [Conf]
  35. Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede
    Side-Channel Leakage Tolerant Architectures. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:204-209 [Conf]
  36. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Extended abstract: a race-free hardware modeling language. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:255-256 [Conf]
  37. Kazuo Sakiyama, Patrick Schaumont, David Hwang, Ingrid Verbauwhede
    Teaching Trade-offs in System-level Design Methodologies. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:62-53 [Conf]
  38. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  39. Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
    A Hardware Virtual Machine for the Networked Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:194-199 [Conf]
  40. Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels, Serge Vernalde, Marc Engels, Ivo Bolsens
    A Technique for Combined Virtual Prototyping and Hardware Design. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:156-161 [Conf]
  41. Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest
    Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:274-290 [Conf]
  42. Patrick Schaumont, Ingrid Verbauwhede
    Domain-Specific Codesign for Embedded Security. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:68-74 [Journal]
  43. Patrick Schaumont, Ingrid Verbauwhede
    A Component-Based Design Environment for ESL Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:338-347 [Journal]
  44. David Hwang, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
    Securing Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Security & Privacy, 2006, v:4, n:2, pp:40-49 [Journal]
  45. Patrick Schaumont, David Hwang, Shenglin Yang, Ingrid Verbauwhede
    Multilevel Design Validation in a Secure Embedded System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1380-1390 [Journal]
  46. Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Durackova
    A new algorithm for elimination of common subexpressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:58-68 [Journal]
  47. Patrick Schaumont, David Hwang, Ingrid Verbauwhede
    Platform-based design for an embedded-fingerprint-authentication device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1929-1936 [Journal]
  48. Ingrid Verbauwhede, Patrick Schaumont
    Skiing the embedded systems mountain. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:529-548 [Journal]
  49. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:131-144 [Journal]
  50. Patrick Schaumont, Doris Ching, Ingrid Verbauwhede
    An interactive codesign environment for domain-specific coprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:70-87 [Journal]
  51. Patrick Schaumont, Kris Tiri
    Masking and Dual-Rail Logic Don't Add Up. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:95-106 [Conf]
  52. Ingrid Verbauwhede, Patrick Schaumont
    Design methods for security and trust. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:672-677 [Conf]
  53. Pengyuan Yu, Patrick Schaumont
    Executing Hardware as Parallel Software for Picoblaze Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  54. Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla
    VT Matrix Multiply Design for MEMOCODE '07. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:95-96 [Conf]
  55. Kris Tiri, Patrick Schaumont
    Changing the Odds Against Masked Logic. [Citation Graph (0, 0)][DBLP]
    Selected Areas in Cryptography, 2006, pp:134-146 [Conf]
  56. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  57. Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
    Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:59-68 [Journal]

  58. Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security. [Citation Graph (, )][DBLP]


  59. Secure FPGA circuits using controlled placement and routing. [Citation Graph (, )][DBLP]


  60. Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. [Citation Graph (, )][DBLP]


  61. Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage. [Citation Graph (, )][DBLP]


  62. pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems. [Citation Graph (, )][DBLP]


  63. Impact and compensation of correlated process variation on ring oscillator based puf. [Citation Graph (, )][DBLP]


  64. Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators. [Citation Graph (, )][DBLP]


  65. Physical unclonable function and true random number generator: a compact and scalable implementation. [Citation Graph (, )][DBLP]


  66. Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits. [Citation Graph (, )][DBLP]


  67. MEMOCODE 2008 Co-Design Contest. [Citation Graph (, )][DBLP]


  68. Intellectual Property Protection for Embedded Sensor Nodes. [Citation Graph (, )][DBLP]


  69. Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors. [Citation Graph (, )][DBLP]


  70. Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform. [Citation Graph (, )][DBLP]


  71. An Analysis of Delay Based PUF Implementations on FPGA. [Citation Graph (, )][DBLP]


  72. A flexible design flow for software IP binding in commodity FPGA. [Citation Graph (, )][DBLP]


  73. Slicing Up a Perfect Hardware Masking Scheme. [Citation Graph (, )][DBLP]


  74. Extended Abstract: Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting. [Citation Graph (, )][DBLP]


  75. Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects. [Citation Graph (, )][DBLP]


  76. Guest Editors' Introduction: Security and Trust in Embedded-Systems Design. [Citation Graph (, )][DBLP]


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