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Kiyoung Choi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:172-182 [Conf]
  2. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Scheduler implementation in MP SoC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:151-156 [Conf]
  3. Jinhwan Jeon, Kiyoung Choi
    Loop Pipelining in Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:361-366 [Conf]
  4. Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi
    High-level synthesis under multi-cycle interconnect delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:662- [Conf]
  5. Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi
    Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:169-174 [Conf]
  6. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha
    An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  7. Youngsoo Shin, Kiyoung Choi
    Narrow bus encoding for low power systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:217-220 [Conf]
  8. Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi
    Worst case execution time analysis for synthesized hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:905-910 [Conf]
  9. Mary Kiemb, Kiyoung Choi
    Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:230-237 [Conf]
  10. Sungtaek Lim, Jihong Kim, Kiyoung Choi
    Scheduling-based code size reduction in processors with indirect addressing mode. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:165-169 [Conf]
  11. Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi
    Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:199-204 [Conf]
  12. Kyoungseok Rha, Kiyoung Choi
    Area-efficient buffer binding based on a novel two-port FIFO structure. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:122-127 [Conf]
  13. Youngsoo Shin, Kiyoung Choi
    Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:3-8 [Conf]
  14. Sungjoo Yoo, Kiyoung Choi
    Optimistic distributed timed cosimulation based on thread simulation model. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:71-75 [Conf]
  15. Sungjoo Yoo, Kiyoung Choi
    Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:100-104 [Conf]
  16. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi
    Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:77-81 [Conf]
  17. Kiyoung Choi, Sun Young Hwang, Tom Blank
    Incremental-in-time Algorithm for Digital Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:501-505 [Conf]
  18. Daehong Kim, Kiyoung Choi
    Power-conscious High Level Synthesis Using Loop Folding. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:441-445 [Conf]
  19. Sanghun Park, Kiyoung Choi
    Performance-Driven Scheduling with Bit-Level Chaining. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:286-291 [Conf]
  20. Youngsoo Shin, Kiyoung Choi
    Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:134-139 [Conf]
  21. Youngsoo Shin, Daehong Kim, Kiyoung Choi
    Schedulability-driven performance analysis of multiple mode embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:495-500 [Conf]
  22. Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi
    A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:363-368 [Conf]
  23. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
    Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20132-20137 [Conf]
  24. Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
    Performance improvement of multi-processor systems cosimulation based on SW analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:749-753 [Conf]
  25. Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi
    Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:12-17 [Conf]
  26. Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi
    Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:663-668 [Conf]
  27. Youngsoo Shin, Kiyoung Choi
    Rate Assignment for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10237-0 [Conf]
  28. Byoungil Jeong, Sungjoo Yoo, Kiyoung Choi
    Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:247- [Conf]
  29. Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi
    Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:320-0 [Conf]
  30. Jong-eun Lee, Kiyoung Choi, Nikil Dutt
    Efficient instruction encoding for automatic instruction set design of configurable ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:649-654 [Conf]
  31. Youngsoo Shin, Kiyoung Choi
    Software synthesis through task decomposition by dependency analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:98-104 [Conf]
  32. Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
    Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:365-368 [Conf]
  33. Kiyoung Choi, KiJong Lee, Jun-Woo Kang
    A Self-Timed Divider Using RSD Number System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:504-507 [Conf]
  34. Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jaehee Won, Kiyoung Choi
    Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:924-927 [Conf]
  35. Mary Kiemb, Kiyoung Choi
    Application-specific configuration of multithreaded processor architecture for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:941-944 [Conf]
  36. Junghwan Choi, Jinhwan Jeon, Kiyoung Choi
    Power minimization of functional units partially guarded computation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:131-136 [Conf]
  37. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    Energy-efficient instruction set synthesis for application-specific processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:330-333 [Conf]
  38. Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
    An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:84-87 [Conf]
  39. Daehong Kim, Dongwan Shin, Kiyoung Choi
    Low power pipelining of linear systems: a common operand centric approach. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:225-230 [Conf]
  40. Dongwan Shin, Kiyoung Choi
    Low power high level synthesis by increasing data correlation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:62-67 [Conf]
  41. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of system level bus. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:127-129 [Conf]
  42. Jae-Hee Won, Kiyoung Choi
    Low power self-timed Radix-2 division (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:210-212 [Conf]
  43. Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek
    Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:310-315 [Conf]
  44. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    An algorithm for mapping loops onto coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:183-188 [Conf]
  45. Nikil D. Dutt, Kiyoung Choi
    Configurable Processors for Embedded Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:1, pp:120-123 [Journal]
  46. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    Compilation Approach for Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:26-33 [Journal]
  47. Sun Young Hwang, Tom Blank, Kiyoung Choi
    Fast functional simulation: an incremental approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:765-774 [Journal]
  48. Sanghun Park, Kiyoung Choi
    Performance-driven high-level synthesis with bit-level chaining andclock selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:199-212 [Journal]
  49. Daehong Kim, Dongwan Shin, Kiyoung Choi
    Pipelining with common operands for power-efficient linear systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1023-1034 [Journal]
  50. Whee Kuk Kim, Kiyoung Choi, Byung-Ju Yi
    A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints. [Citation Graph (0, 0)][DBLP]
    ICRA, 2004, pp:2801-2807 [Conf]
  51. Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya
    Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:195-201 [Conf]
  52. Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi
    Buffer Size Reduction through Control-Flow Decomposition. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:183-190 [Conf]
  53. Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi
    Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:50-57 [Conf]
  54. Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi
    Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  55. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    Instruction set synthesis with efficient instruction encoding for configurable processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]
  56. KiJong Lee, Kiyoung Choi
    Self-timed divider based on RSD number system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:292-295 [Journal]
  57. Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha
    Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:492-502 [Journal]
  58. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of application-specific systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:377-383 [Journal]
  59. Youngsoo Shin, Kiyoung Choi, Young-hoon Chang
    Narrow bus encoding for low-power DSP systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:656-660 [Journal]

  60. Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. [Citation Graph (, )][DBLP]


  61. Communication Architecture Synthesis of Cascaded Bus Matrix. [Citation Graph (, )][DBLP]


  62. Code decomposition and recomposition for enhancing embedded software performance. [Citation Graph (, )][DBLP]


  63. Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. [Citation Graph (, )][DBLP]


  64. Entry control in network-on-chip for memory power reduction. [Citation Graph (, )][DBLP]


  65. A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. [Citation Graph (, )][DBLP]


  66. Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  67. Memory-Centric Communication Architecture for Reconfigurable Computing. [Citation Graph (, )][DBLP]


  68. Coarse-grained reconfigurable architecture for multiple application domains: a case study. [Citation Graph (, )][DBLP]


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