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Nikil D. Dutt :
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Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. [Citation Graph (0, 0)][DBLP ] ASAP, 2003, pp:172-182 [Conf ] Nikil D. Dutt , Alexandru Nicolau , Hiroyuki Tomiyama , Ashok Halambi New directions in compiler technology for embedded systems (embedded tutorial). [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:409-414 [Conf ] Pradip K. Jha , Nikil D. Dutt , Sri Parameswaran Reclocking for high-level synthesis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1995, pp:- [Conf ] Prabhat Mishra , Ashok Halambi , Peter Grun , Nikil D. Dutt , Alexandru Nicolau , Hiroyuki Tomiyama Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:458-466 [Conf ] Sudeep Pasricha , Nikil D. Dutt , Mohamed Ben-Romdhane Constraint-driven bus matrix synthesis for MPSoC. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:30-35 [Conf ] Jaewon Seo , Nikil D. Dutt A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:836-841 [Conf ] Aviral Shrivastava , Nikil D. Dutt Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:475-477 [Conf ] Partha Biswas , Nikil D. Dutt Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. [Citation Graph (0, 0)][DBLP ] CASES, 2003, pp:104-112 [Conf ] Hyunok Oh , Nikil D. Dutt , Soonhoi Ha Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP ] CASES, 2005, pp:157-165 [Conf ] Roger P. Ang , Nikil D. Dutt A Representation for the Binding of RT-Component Functionality to HDL Behavior. [Citation Graph (0, 0)][DBLP ] CHDL, 1993, pp:263-280 [Conf ] Peter Grun , Florin Balasa , Nikil D. Dutt Memory size estimation for multimedia applications. [Citation Graph (0, 0)][DBLP ] CODES, 1998, pp:145-149 [Conf ] Sudarshan Banerjee , Nikil D. Dutt Efficient search space exploration for HW-SW partitioning. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:122-127 [Conf ] Mahesh Mamidipaka , Kamal S. Khouri , Nikil D. Dutt , Magdy S. Abadir Analytical models for leakage power estimation of memory array structures. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:146-151 [Conf ] Hyunok Oh , Nikil D. Dutt , Soonhoi Ha Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2005, pp:51-56 [Conf ] Sudeep Pasricha , Nikil D. Dutt , Mohamed Ben-Romdhane Fast exploration of bus-based on-chip communication architectures. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:242-247 [Conf ] Mehrdad Reshadi , Nikhil Bansal , Prabhat Mishra , Nikil D. Dutt An efficient retargetable framework for instruction-set simulation. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2003, pp:13-18 [Conf ] Aviral Shrivastava , Eugene Earlie , Nikil D. Dutt , Alexandru Nicolau Operation tables for scheduling in the presence of incomplete bypassing. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:194-199 [Conf ] Aviral Shrivastava , Eugene Earlie , Nikil D. Dutt , Alexandru Nicolau Aggregating processor free time for energy reduction. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2005, pp:154-159 [Conf ] Hiroyuki Tomiyama , Nikil D. Dutt Program path analysis to bound cache-related preemption delay in preemptive real-time systems. [Citation Graph (0, 0)][DBLP ] CODES, 2000, pp:67-71 [Conf ] Aseem Gupta , Nikil D. Dutt , Fadi J. Kurdahi , Kamal S. Khouri , Magdy S. Abadir Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2006, pp:118-123 [Conf ] Sudeep Pasricha , Young-Hwan Park , Fadi J. Kurdahi , Nikil D. Dutt System-level power-performance trade-offs in bus matrix communication architecture synthesis. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2006, pp:300-305 [Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:335-340 [Conf ] Nikil D. Dutt , David Agnew , Raul Camposano , Antun Domic , Manfred Wiesel , Hiroto Yasuura Design Reuse: Fact or Fiction? (Panel). [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:562- [Conf ] Nikil D. Dutt , Daniel Gajski Designer Controlled Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:754-757 [Conf ] Nikil D. Dutt , Tedd Hadley , Daniel Gajski An Intermediate Representation for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:14-19 [Conf ] Nikil D. Dutt , James R. Kipps Bridging High-Level Synthesis to RTL Technology Libraries. [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:526-529 [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Memory aware compilation through accurate timing extraction. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:316-321 [Conf ] Sumit Gupta , Nick Savoiu , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau , Timothy Kam , Michael Kishinevsky , Shai Rotem Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:898-903 [Conf ] Sumit Gupta , Nick Savoiu , Sunwoo Kim , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Speculation Techniques for High Level Synthesis of Control Intensive Designs. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:269-272 [Conf ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt Minimization of Memory Traffic in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:149-154 [Conf ] Sudeep Pasricha , Nikil D. Dutt , Mohamed Ben-Romdhane Extending the transaction level modeling approach for fast communication architecture exploration. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:113-118 [Conf ] Sudeep Pasricha , Nikil D. Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:565-570 [Conf ] Mehrdad Reshadi , Prabhat Mishra , Nikil D. Dutt Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:758-763 [Conf ] Haigeng Wang , Nikil D. Dutt , Alexandru Nicolau , Kai-Yeung Siu High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:336-342 [Conf ] Steven Novack , Alexandru Nicolau , Nikil D. Dutt A Unified code generation approach using mutation scheduling. [Citation Graph (0, 0)][DBLP ] Code Generation for Embedded Processors, 1994, pp:203-218 [Conf ] Ana Azevedo , Ilya Issenin , Radu Cornea , Rajesh Gupta , Nikil D. Dutt , Alexander V. Veidenbaum , Alexandru Nicolau Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:168-175 [Conf ] Hans Van Antwerpen , Nikil D. Dutt , Rajesh K. Gupta , Shivajit Mohapatra , Cristiano Pereira , Nalini Venkatasubramanian , Ralph von Vignau Energy-Aware System Design for Wireless Multimedia. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1124-1131 [Conf ] Partha Biswas , Sudarshan Banerjee , Nikil D. Dutt , Laura Pozzi , Paolo Ienne ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1246-1251 [Conf ] Partha Biswas , Nikil D. Dutt , Paolo Ienne , Laura Pozzi Automatic identification of application-specific functional units with architecturally visible storage. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:212-217 [Conf ] Francky Catthoor , Nikil D. Dutt , Christoforos E. Kozyrakis How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:426-0 [Conf ] Radu Cornea , Alexandru Nicolau , Nikil D. Dutt Software annotations for power optimization on mobile devices. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:684-689 [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Access pattern based local memory customization for low power embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:778-784 [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Memory System Connectivity Exploration. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:894-901 [Conf ] Sumit Gupta , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10270-10275 [Conf ] Ashok Halambi , Radu Cornea , Peter Grun , Nikil D. Dutt , Alexandru Nicolau Architecture Exploration of Parameterizable EPIC SOC Architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:748- [Conf ] Ashok Halambi , Peter Grun , V. Ganesh , Asheesh Khare , Nikil D. Dutt , Alexandru Nicolau EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:485-490 [Conf ] Ashok Halambi , Aviral Shrivastava , Partha Biswas , Nikil D. Dutt , Alexandru Nicolau An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:402-408 [Conf ] Ilya Issenin , Nikil D. Dutt FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:808-813 [Conf ] Mahesh Mamidipaka , Nikil D. Dutt On-chip Stack Based Memory Organization for Low Power Embedded Architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:11082-11089 [Conf ] Prabhat Mishra , Nikil D. Dutt Functional Coverage Driven Test Generation for Validation of Pipelined Processors. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:678-683 [Conf ] Prabhat Mishra , Nikil D. Dutt , Alexandru Nicolau , Hiroyuki Tomiyama Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:36-43 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Data Cache Sizing for Embedded Processor Applications. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:925-926 [Conf ] Sudeep Pasricha , Nikil D. Dutt COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:700-705 [Conf ] Mehrdad Reshadi , Nikil D. Dutt Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:786-791 [Conf ] Aviral Shrivastava , Nikil D. Dutt , Alexandru Nicolau , Eugene Earlie PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1264-1269 [Conf ] Prabhat Mishra , Nikil D. Dutt Functional Validation of Programmable Architectures. [Citation Graph (0, 0)][DBLP ] DSD, 2004, pp:12-19 [Conf ] Sudeep Pasricha , Shivajit Mohapatra , Manev Luthra , Nikil D. Dutt , Nalini Venkatasubramanian Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices. [Citation Graph (0, 0)][DBLP ] ESTImedia, 2003, pp:11-17 [Conf ] Hiroyuki Tomiyama , Hiroaki Takada , Nikil D. Dutt Data Organization Exploration for Low-Energy Address Buses. [Citation Graph (0, 0)][DBLP ] ESTImedia, 2003, pp:128-133 [Conf ] Asheesh Khare , Nicolae Savoiu , Ashok Halambi , Peter Grun , Nikil D. Dutt , Alexandru Nicolau V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1196-1203 [Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] FCCM, 2005, pp:273-274 [Conf ] Nikhil Bansal , Sumit Gupta , Nikil D. Dutt , Alexandru Nicolau , Rajesh K. Gupta Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] FPL, 2004, pp:891-899 [Conf ] Sudarshan Banerjee , Nikil D. Dutt FIFO power optimization for on-chip networks. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2004, pp:187-191 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt Memory Architectures for Embedded Systems-On-Chip. [Citation Graph (0, 0)][DBLP ] HiPC, 2002, pp:647-662 [Conf ] Roger P. Ang , Nikil D. Dutt Equivalent design representations and transformations for interactive scheduling. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:332-335 [Conf ] Nikil D. Dutt , Eric Foster Design of a set-top box system on a chip (abstract). [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:608- [Conf ] Nikil D. Dutt , Brian Kelley On the rapid prototyping and design of a wireless communication system on a chip (abstract). [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:609- [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau MIST: An Algorithm for Memory Miss Traffic Management. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:431-437 [Conf ] Soren Hein , Vijay Nagasamy , Bernhard Rohfleisch , Christoforos E. Kozyrakis , Nikil D. Dutt , Francky Catthoor Embedded memories in system design - from technology to systems architecture. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:1- [Conf ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt Integrating program transformations in the memory-based synthesis of image and video algorithms. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:27-30 [Conf ] Mahesh Mamidipaka , Kamal S. Khouri , Nikil D. Dutt , Magdy S. Abadir IDAP: A Tool for High Level Power Estimation of Custom Array Structures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:113-119 [Conf ] Lode Nachtergaele , Vivek Tiwari , Nikil D. Dutt System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:569-573 [Conf ] Seong Yong Ohm , Fadi J. Kurdahi , Nikil D. Dutt Comprehensive lower bound estimation from behavioral descriptions. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:182-187 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Exploiting off-chip memory access modes in high-level synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:333-340 [Conf ] Jaewon Seo , Taewhan Kim , Nikil D. Dutt Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:450-455 [Conf ] Manev Luthra , Sumit Gupta , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Interface Synthesis using Memory Mapping for an FPGA Platform. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:140-145 [Conf ] Preeti Ranjan Panda , Hiroshi Nakamura , Nikil D. Dutt , Alexandru Nicolau A Data Alignment Technique for Improving Cache Performance. [Citation Graph (0, 0)][DBLP ] ICCD, 1997, pp:587-592 [Conf ] Mehrdad Reshadi , Nikil D. Dutt Reducing Compilation Time Overhead in Compiled Simulators. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:151-0 [Conf ] Nikil D. Dutt LEGEND: A Language for Generic Component Library Description. [Citation Graph (0, 0)][DBLP ] ICCL, 1990, pp:198-207 [Conf ] Minyoung Kim , Hyunok Oh , Nikil D. Dutt , Alexandru Nicolau , Nalini Venkatasubramanian Probability Based Power Aware Error Resilient Coding. [Citation Graph (0, 0)][DBLP ] ICDCS Workshops, 2005, pp:307-313 [Conf ] Liang Cheng , Stefano Bossi , Shivajit Mohapatra , Magda El Zarki , Nalini Venkatasubramanian , Nikil D. Dutt Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices. [Citation Graph (0, 0)][DBLP ] ICN (1), 2005, pp:662-671 [Conf ] Andrea Capitanio , Nikil D. Dutt , Alexandru Nicolau Partitioning of Variables for Multiple-Register-File VLIW Architectures. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1994, pp:298-301 [Conf ] Daniel Gajski , Nikil D. Dutt Benchmarking and the Art of Syntesis Tool Comparison. [Citation Graph (0, 0)][DBLP ] Synthesis for Control Dominated Circuits, 1992, pp:439-453 [Conf ] Prabhat Mishra , Nikil D. Dutt Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. [Citation Graph (0, 0)][DBLP ] DIPES, 2002, pp:81-90 [Conf ] Ashok Halambi , Nikil D. Dutt , Alexandru Nicolau Customizing Software Toolkits for Embedded Systems-On-Chip. [Citation Graph (0, 0)][DBLP ] DIPES, 2000, pp:87-98 [Conf ] Andrea Capitanio , Nikil D. Dutt , Alexandru Nicolau Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring. [Citation Graph (0, 0)][DBLP ] IFIP PACT, 1994, pp:319-322 [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Aggressive Memory-Aware Compilation. [Citation Graph (0, 0)][DBLP ] Intelligent Memory Systems, 2000, pp:147-151 [Conf ] Radu Cornea , Nikil D. Dutt , Rajesh K. Gupta , Ingolf Krüger , Alexandru Nicolau , Douglas C. Schmidt , Sandeep K. Shukla FORGE: A Framework for Optimization of Distributed Embedded Systems Software. [Citation Graph (0, 0)][DBLP ] IPDPS, 2003, pp:208- [Conf ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt , Ken Kennedy A Method for Register Allocation to Loops in Multiple Register File Architectures. [Citation Graph (0, 0)][DBLP ] IPPS, 1996, pp:28-33 [Conf ] Shivajit Mohapatra , Radu Cornea , Hyunok Oh , Kyoungwoo Lee , Minyoung Kim , Nikil D. Dutt , Rajesh Gupta , Alexandru Nicolau , Sandeep K. Shukla , Nalini Venkatasubramanian A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems. [Citation Graph (0, 0)][DBLP ] IPDPS, 2005, pp:- [Conf ] Preeti Ranjan Panda , Hiroshi Nakamura , Nikil D. Dutt , Alexandru Nicolau Improving cache Performance Through Tiling and Data Alignment. [Citation Graph (0, 0)][DBLP ] IRREGULAR, 1997, pp:167-185 [Conf ] Ann Gordon-Ross , Frank Vahid , Nikil D. Dutt Fast configurable-cache tuning with a unified second-level cache. [Citation Graph (0, 0)][DBLP ] ISLPED, 2005, pp:323-326 [Conf ] Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt Energy-efficient instruction set synthesis for application-specific processors. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:330-333 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt Low-power mapping of behavioral arrays to multiple memories. [Citation Graph (0, 0)][DBLP ] ISLPED, 1996, pp:289-292 [Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau APEX. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:25-32 [Conf ] Peter Grun , Ashok Halambi , Nikil D. Dutt , Alexandru Nicolau RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. [Citation Graph (0, 0)][DBLP ] ISSS, 1999, pp:44-50 [Conf ] Sumit Gupta , Nick Savoiu , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Conditional speculation and its effects on performance and area for high-level snthesis. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:171-176 [Conf ] Nikil D. Dutt , Daniel S. Hirschberg , Mahesh Mamidipaka Efficient Power Reduction Techniques for Time Multiplexed Address Buses. [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:207-212 [Conf ] Alexandru Nicolau , Nikil D. Dutt , Rajesh Gupta , Nick Savoiu , Mehrdad Reshadi , Sumit Gupta Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:261-266 [Conf ] Prabhat Mishra , Nikil D. Dutt , Alexandru Nicolau Functional abstraction driven design space exploration of heterogeneous programmable architectures. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:256-261 [Conf ] Alexandru Nicolau , Nikil D. Dutt , Aviral Shrivastava , Partha Biswas , Ashok Halambi A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:120-125 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Memory Organization for Improved Data Cache Performance in Embedded Processors. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:90-95 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt 1995 high level synthesis design repository. [Citation Graph (0, 0)][DBLP ] ISSS, 1995, pp:170-174 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Architectural Exploration and Optimization of Local Memory in Embedded Systems. [Citation Graph (0, 0)][DBLP ] ISSS, 1997, pp:90-0 [Conf ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt Copy Elimination for Parallelizing Compilers. [Citation Graph (0, 0)][DBLP ] LCPC, 1998, pp:275-289 [Conf ] Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt An algorithm for mapping loops onto coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] LCTES, 2003, pp:183-188 [Conf ] Sanghyun Park , Aviral Shrivastava , Nikil D. Dutt , Alexandru Nicolau , Yunheung Paek , Eugene Earlie Bypass aware instruction scheduling for register file power reduction. [Citation Graph (0, 0)][DBLP ] LCTES, 2006, pp:173-181 [Conf ] Andrea Capitanio , Nikil D. Dutt , Alexandru Nicolau Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. [Citation Graph (0, 0)][DBLP ] MICRO, 1992, pp:292-300 [Conf ] Shivajit Mohapatra , Radu Cornea , Nikil D. Dutt , Alexandru Nicolau , Nalini Venkatasubramanian Integrated power management for video streaming to mobile handheld devices. [Citation Graph (0, 0)][DBLP ] ACM Multimedia, 2003, pp:582-591 [Conf ] Brian Kahne , Aseem Gupta , Peter Wilson , Nikil D. Dutt An Introduction to the Plasma Language. [Citation Graph (0, 0)][DBLP ] MTV, 2005, pp:12-22 [Conf ] Prabhat Mishra , Nikil D. Dutt A Methodology for Validation of Microprocessors using Equivalence Checking. [Citation Graph (0, 0)][DBLP ] MTV, 2003, pp:83-88 [Conf ] Prabhat Mishra , Nikil D. Dutt , Yaron Kashai Functional Verification of Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP ] MTV, 2004, pp:79-84 [Conf ] Marcio Buss , Tony Givargis , Nikil D. Dutt Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores. [Citation Graph (0, 0)][DBLP ] RTSS, 2003, pp:275-0 [Conf ] Partha Biswas , Sudarshan Banerjee , Nikil D. Dutt , Paolo Ienne , Laura Pozzi Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:651-656 [Conf ] Sumit Gupta , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:461-466 [Conf ] David J. Kolson , Nikil D. Dutt , Alexandru Nicolau Ultra Fine-Grain Template-Driven Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:25-28 [Conf ] Pradip K. Jha , Nikil D. Dutt Rapid Technology Projection for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:155-158 [Conf ] Pradip K. Jha , Champaka Ramachandran , Nikil D. Dutt , Fadi J. Kurdahi An Empirical Study on the Effects of Physical Design in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:11-16 [Conf ] Mahesh Mamidipaka , Nikil D. Dutt , Kamal S. Khouri A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:320-0 [Conf ] Prabhat Mishra , Peter Grun , Nikil D. Dutt , Alexandru Nicolau Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:70-75 [Conf ] Prabhat Mishra , Hiroyuki Tomiyama , Ashok Halambi , Peter Grun , Nikil D. Dutt , Alexandru Nicolau Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:458-0 [Conf ] Preeti Ranjan Panda , Nikil D. Dutt Behavioral Array Mapping into Multiport Memories Targeting Low Power. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:268-273 [Conf ] Haigeng Wang , Nikil D. Dutt , Alexandru Nicolau Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1993, pp:198-201 [Conf ] Aseem Gupta , Nikil D. Dutt , Fadi J. Kurdahi , Kamal S. Khouri , Magdy S. Abadir STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:559-564 [Conf ] Nikil D. Dutt , Kiyoung Choi Configurable Processors for Embedded Computing. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2003, v:36, n:1, pp:120-123 [Journal ] Francky Catthoor , Koen Danckaert , Sven Wuytack , Nikil D. Dutt Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2001, v:18, n:3, pp:70-82 [Journal ] Nikil D. Dutt , Daniel D. Gajski Design Synthesis and Silicon Compilation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1990, v:7, n:6, pp:8-23 [Journal ] Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt Compilation Approach for Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2003, v:20, n:1, pp:26-33 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau , Francky Catthoor , Arnout Vandecappelle , Erik Brockmeyer , Chidamber Kulkarni , Eddy de Greef Data Memory Organization and Optimizations in Application-Specific Systems. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2001, v:18, n:3, pp:56-68 [Journal ] Sudeep Pasricha , Manev Luthra , Shivajit Mohapatra , Nikil D. Dutt , Nalini Venkatasubramanian Dynamic Backlight Adaptation for Low-Power Handheld Devices. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:5, pp:398-405 [Journal ] Partha Biswas , Nikil D. Dutt Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2005, v:54, n:10, pp:1216-1226 [Journal ] Preeti Ranjan Panda , Hiroshi Nakamura , Nikil D. Dutt , Alexandru Nicolau Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1999, v:48, n:2, pp:142-149 [Journal ] Sumit Gupta , Nicolae Savoiu , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Using global code motions to improve the quality of results for high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:302-312 [Journal ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt Elimination of redundant memory traffic in high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1354-1364 [Journal ] Mahesh Mamidipaka , Kamal S. Khouri , Nikil D. Dutt , Magdy S. Abadir IDAP: a tool for high-level power estimation of custom array structures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1361-1369 [Journal ] Seong Yong Ohm , Fadi J. Kurdahi , Nikil D. Dutt A unified lower bound estimation technique for high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:458-472 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Incorporating DRAM access modes into high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:96-109 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Local memory exploration and optimization in embedded systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:3-13 [Journal ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Access pattern-based memory and connectivity architecture exploration. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:33-73 [Journal ] Sumit Gupta , Rajesh K. Gupta , Nikil D. Dutt , Alexandru Nicolau Coordinated parallelizing compiler optimizations and high-level synthesis. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:441-470 [Journal ] Pradip K. Jha , Nikil D. Dutt High-level library mapping for memories. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:566-603 [Journal ] Nikil D. Dutt Editorial. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:1-2 [Journal ] Nikil D. Dutt Editorial. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:1-2 [Journal ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt , Ken Kennedy Optimal register assignment to loops for embedded code generation. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:2, pp:251-279 [Journal ] Aviral Shrivastava , Partha Biswas , Ashok Halambi , Nikil D. Dutt , Alexandru Nicolau Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:123-146 [Journal ] Preeti Ranjan Panda , Francky Catthoor , Nikil D. Dutt , Koen Danckaert , Erik Brockmeyer , Chidamber Kulkarni , Arnout Vandecappelle , Per Gunnar Kjeldsberg Data and memory optimization techniques for embedded systems. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:149-206 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:682-704 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Memory data organization for improved cache performance in embedded processor applications. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:384-409 [Journal ] Sudeep Pasricha , Nikil D. Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane FABSYN: floorplan-aware bus architecture synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:241-253 [Journal ] Aviral Shrivastava , Eugene Earlie , Nikil D. Dutt , Alexandru Nicolau Retargetable pipeline hazard detection for partially bypassed processors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:791-801 [Journal ] Partha Biswas , Sudarshan Banerjee , Nikil D. Dutt , Laura Pozzi , Paolo Ienne ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal ] Arun Kejariwal , Sumit Gupta , Alexandru Nicolau , Nikil D. Dutt , Rajesh K. Gupta Energy efficient watermarking on mobile devices using proxy-based partitioning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:625-636 [Journal ] Minyoung Kim , Mark-Oliver Stehr , Carolyn L. Talcott , Nikil D. Dutt , Nalini Venkatasubramanian A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] FMOODS, 2007, pp:285-300 [Conf ] Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt Instruction set synthesis with efficient instruction encoding for configurable processors. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1189-1202 [Journal ] Pradip K. Jha , Nikil D. Dutt Rapid estimation for parameterized components in high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:296-303 [Journal ] Pradip K. Jha , Nikil D. Dutt High-level library mapping for arithmetic components. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:157-169 [Journal ] Preeti Ranjan Panda , Nikil D. Dutt Low-power memory mapping through reducing address bus activity. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:309-320 [Journal ] Allen C.-H. Wu , Nikil D. Dutt Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:469-471 [Journal ] Mahesh Mamidipaka , Daniel S. Hirschberg , Nikil D. Dutt Adaptive low-power address encoding techniques using self-organizing lists. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:827-834 [Journal ] Peter Grun , Ashok Halambi , Nikil D. Dutt , Alexandru Nicolau RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:731-737 [Journal ] LEAF: A System Level Leakage-Aware Floorplanner for SoCs. [Citation Graph (, )][DBLP ] Library mapping for memories. [Citation Graph (, )][DBLP ] Efficient utilization of scratch-pad memory in embedded processor applications. [Citation Graph (, )][DBLP ] Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. [Citation Graph (, )][DBLP ] A framework for memory-aware multimedia application mapping on chip-multiprocessors. [Citation Graph (, )][DBLP ] Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP ] PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. [Citation Graph (, )][DBLP ] Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. [Citation Graph (, )][DBLP ] Search in 0.019secs, Finished in 0.847secs