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Vinoo Srinivasan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri
    Rapid Prototyping of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:303-312 [Conf]
  2. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
    Hardware Software Partitioning with Integrated Hardware Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:28-35 [Conf]
  3. Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
    An Effective Design System for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:312-313 [Conf]
  4. Vinoo Srinivasan, Ranga Vemuri
    Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:272-0 [Conf]
  5. Vinoo Srinivasan, Ranga Vemuri
    Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:253- [Conf]
  6. Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
    Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:924-931 [Conf]
  7. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
    An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:31-36 [Conf]
  8. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeffrey Walrath
    Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:588-596 [Conf]
  9. Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri
    A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:212-219 [Conf]
  10. Vinoo Srinivasan, Ranga Vemuri
    A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:435-441 [Conf]

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