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Rong Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rong Lin, Stephan Olariu
    A simple array processor for binary prefix sums. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:113-0 [Conf]
  2. Kendra Cooper, João W. Cangussu, Rong Lin, Ganesan Sankaranarayanan, Ragouramane Soundararadjane, W. Eric Wong
    An Empirical Study on the Specification and Selection of Components Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    CBSE, 2005, pp:155-170 [Conf]
  3. Rong Lin, Stephan Olariu
    Computing the Inner Product on Reconfigurable Buses with Shift Switching. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1992, pp:181-192 [Conf]
  4. Rong Lin
    Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:2456-2463 [Conf]
  5. Rong Lin, Kevin E. Kerr, André S. Botha
    A Novel Approach for CMOS Parallel Counter Design. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1112-1119 [Conf]
  6. Rong Lin, Stephan Olariu
    Fast Parallel Algorithms for Cographs. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1990, pp:176-189 [Conf]
  7. Rong Lin, Martin Margala
    Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:172-177 [Conf]
  8. Rong Lin
    Convolution Computation on Shift Switching Buses. [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1994, pp:120-129 [Conf]
  9. Rong Lin, Stephan Olariu
    A Simple Optimal Parallel Algorithm to Solve the Lowest Common Ancestor Problem. [Citation Graph (0, 0)][DBLP]
    ICCI, 1991, pp:455-461 [Conf]
  10. Dharmavani Bhagavathi, Venkatavasu Bokka, Himabindu Gurla, Rong Lin, Stephan Olariu, James L. Schwing, W. Shen, Larry Wilson
    Time-Optimal Multiple Rank Computations on Meshes with Multiple Broadcasting. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:35-38 [Conf]
  11. Dharmavani Bhagavathi, Himabindu Gurla, Stephan Olariu, Rong Lin, James L. Schwing, Jingyuan Zhang
    Square Meshes Are Not Optimal For Convex Hull Computation. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:307-310 [Conf]
  12. Rong Lin, Stephan Olariu
    A Fast Parallel Algorithm to Compute Path Functions for Cographs. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1991, pp:263-266 [Conf]
  13. Rong Lin
    Reconfigurable Buses with Shift Switching - VLSI RADIX Sort. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:2-9 [Conf]
  14. Rong Lin
    A run-time reconfigurable array of multipliers architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:143- [Conf]
  15. Rong Lin
    Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  16. Rong Lin
    A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:182- [Conf]
  17. Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya
    A Scalable VLSI Architecture for Binary Prefix Sums. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:333-337 [Conf]
  18. Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya
    Scalable Hardware-Algorithms for Binary Prefix Sums. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:634-642 [Conf]
  19. Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya
    An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:273-0 [Conf]
  20. Rong Lin, James L. Schwing
    A Non-binary Parallel Arithmetic Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:149-154 [Conf]
  21. Rong Lin
    A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:321-328 [Conf]
  22. Rong Lin
    Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:325-330 [Conf]
  23. Rong Lin
    Reconfigurable buses with shift switches for fast final additions of parallel multipliers. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1997, pp:513-521 [Conf]
  24. Rong Lin, Stephan Olariu
    On the parallel recognition of some tree-representable graphs. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:6-13 [Conf]
  25. Rong Lin, Stephan Olariu
    A Fast Parallel Algorithm to Recognize P4-sparse Graphs. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1998, v:81, n:1-3, pp:191-215 [Journal]
  26. Rong Lin
    Fast Algorithms for Lowest Common Ancestors on a Processor Array with Reconfigurable Buses. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1991, v:40, n:4, pp:223-230 [Journal]
  27. Rong Lin, Stephan Olariu
    A Fast Parallel, Algorithm to Recognize, Partitionable Graphs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1990, v:36, n:3, pp:153-157 [Journal]
  28. Rong Lin, Stephan Olariu
    An NC Recognition Algorithm for Cographs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:13, n:1, pp:76-90 [Journal]
  29. Rong Lin, Stephan Olariu
    An Optimal Parallel Matching Algorithm for Cographs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:1, pp:26-36 [Journal]
  30. Rong Lin, Stephan Olariu
    A fast cost-optimal parallel algorithm for the lowest common ancestor problem. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:5, pp:511-516 [Journal]
  31. Rong Lin, Stephan Olariu, James L. Schwing, Jingyuan Zhang
    Simulating Enhanced Meshes, with Applications. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1993, v:3, n:, pp:59-70 [Journal]
  32. Rong Lin, Stephan Olariu, James L. Schwing, Jingyuan Zhang
    Computing on Reconfigurable Buses - A New Computational Paradigm. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:465-476 [Journal]
  33. Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya
    An Efficient Parallel Prefix Sums Architecture with Domino Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:9, pp:922-931 [Journal]
  34. Rong Lin, Stephan Olariu
    Reconfigurable Buses with Shift Switching: Concepts and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:1, pp:93-102 [Journal]
  35. Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang
    The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:3, pp:266-280 [Journal]
  36. Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya
    Scalable Hardware-Algorithms for Binary Prefix Sums. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:8, pp:838-850 [Journal]
  37. Rong Lin
    Inner Product Processor Designs Using High-Performance, Non-Binary Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:345-350 [Conf]
  38. Rong Lin, Stephan Olariu
    Efficient VLSI architectures for Columnsort. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:135-138 [Journal]
  39. Rong Lin
    Reconfigurable parallel inner product processor architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:261-272 [Journal]

  40. An optimal parallel matching algorithm for cographs. [Citation Graph (, )][DBLP]


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