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Rolf Ernst: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amilcar do Carmo Lucas, Rolf Ernst
    An Image Processor for Digital Film. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:219-224 [Conf]
  2. Rolf Ernst, Ahmed Amine Jerraya
    embedded system design with multiple languages: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:391-396 [Conf]
  3. Jörg Henkel, Rolf Ernst
    High-Level Estimation Techniques for Usage in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:353-360 [Conf]
  4. Peter Lüders, Rolf Ernst
    Verbesserung der Benutzeroberfläche von CAD-Systemen durch automatisches Bildschirmlayout. [Citation Graph (0, 0)][DBLP]
    Rechnerunterstütztes Entwerfen und Konstruieren (CAD), 1992, pp:77-92 [Conf]
  5. Stefan Stille, Rolf Ernst
    Using Adaptive Layout Calculation to Handle the Visual Chaos in GUIs. [Citation Graph (0, 0)][DBLP]
    CADUI, 1999, pp:185-198 [Conf]
  6. Razvan Racu, Arne Hamann, Rolf Ernst, Bren Mochocki, Xiaobo Sharon Hu
    Methods for power optimization in distributed embedded systems with real-time requirements. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:379-388 [Conf]
  7. Thomas Benner, Rolf Ernst
    An Approach to Mixed Systems Co-Synthesis. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:9-14 [Conf]
  8. Reinaldo A. Bergamaschi, Grant Martin, Wayne Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris
    The future of system-level design: can we find the right solutions to the right problems at the right time? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:231- [Conf]
  9. Reinhard Gerndt, Rolf Ernst
    An Event-Driven Multi-Threading Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:29-34 [Conf]
  10. Jörg Henkel, Rolf Ernst
    The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:52-61 [Conf]
  11. Dirk Herrmann, Jörg Henkel, Rolf Ernst
    An approach to the adaptation of estimated cost parameters in the COSYMA system. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:100-107 [Conf]
  12. Marek Jersak, Kai Richter, Rafik Henia, Rolf Ernst, Frank Slomka
    Transformation of SDL specifications for system-level timing analysis. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:121-126 [Conf]
  13. Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    Scheduling hardware/software systems using symbolic techniques. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:173-177 [Conf]
  14. Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele
    Combining multiple models of computation for scheduling and allocation. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:9-13 [Conf]
  15. Arne Hamann, Razvan Racu, Rolf Ernst
    A formal approach to robustness maximization of complex heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:40-45 [Conf]
  16. Simon Schliecker, Matthias Ivers, Rolf Ernst
    Integrated analysis of communicating tasks in MPSoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:288-293 [Conf]
  17. Sven Heithecker, Rolf Ernst
    Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:575-578 [Conf]
  18. Jörg Henkel, Rolf Ernst
    A Hardware/Software Partitioner Using a Dynamically Determined Granularity. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:691-696 [Conf]
  19. Marek Jersak, Rolf Ernst
    Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:454-459 [Conf]
  20. Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich
    Representation of Function Variants for Embedded System Optimization and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:517-522 [Conf]
  21. Kai Richter, Dirk Ziegenbein, Marek Jersak, Rolf Ernst
    Model composition for scheduling analysis in platform design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:287-292 [Conf]
  22. Fabian Wolf, Jan Staschulat, Rolf Ernst
    Associative caches in formal software timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:622-627 [Conf]
  23. Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers
    The Future of Flexible HW Platform Architectures Panel Discussion. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:634-0 [Conf]
  24. Arne Hamann, Rolf Ernst
    TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:312-317 [Conf]
  25. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
    System Design for Flexibility. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:854-861 [Conf]
  26. Rafik Henia, Rolf Ernst
    Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:480-485 [Conf]
  27. Rafik Henia, Rolf Ernst
    Improved offset-analysis using multiple timing-references. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:450-455 [Conf]
  28. Ahmed Amine Jerraya, Rolf Ernst
    Multi-Language System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:696-0 [Conf]
  29. Marek Jersak, Rafik Henia, Rolf Ernst
    Context-Aware Performance Analysis for Efficient Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1046-1051 [Conf]
  30. Marek Jersak, Kai Richter, Rolf Ernst, Jörn-Christian Braam, Zheng-Yu Jiang, Fabian Wolf
    Formal Methods for Integration of Automotive Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20045-20050 [Conf]
  31. Judita Kruse, Clive Thomsen, Rolf Ernst, Thomas Volling, Thomas Spengler
    Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:938-943 [Conf]
  32. Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller
    A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:194-199 [Conf]
  33. Kai Richter, Rolf Ernst
    Event Model Interfaces for Heterogeneous System Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:506-513 [Conf]
  34. Kai Richter, Rolf Ernst
    How OEMs and suppliers can face the network integration challenges. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:183-188 [Conf]
  35. Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabian Wolf
    Context Sensitive Performance Analysis of Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:165-170 [Conf]
  36. Ken Tindell, Hermann Kopetz, Fabian Wolf, Rolf Ernst
    Safe Automotive Software Development. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10616-10623 [Conf]
  37. Rolf Ernst
    Combining Languages in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:62-0 [Conf]
  38. Jan Staschulat, Simon Schliecker, Rolf Ernst
    Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2005, pp:41-48 [Conf]
  39. Jan Staschulat, Rolf Ernst
    Multiple process execution in cache related preemption delay analysis. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:278-286 [Conf]
  40. K. Henriss, Peter Rüffer, Rolf Ernst, S. Hasenzahl
    A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:285-286 [Conf]
  41. Sven Heithecker, Rolf Ernst
    An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:277- [Conf]
  42. Thomas Benner, Rolf Ernst, Ingo Könenkamp, Ulrich Holtmann, P. Schüler, H.-C. Schaub, N. Serafimov
    FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:251-258 [Conf]
  43. Rolf Ernst
    Rapid Prototyping für integrierte Steuerungssysteme mit harten Zeitbedingungen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1997, pp:121-122 [Conf]
  44. Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele
    SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2005, pp:693-697 [Conf]
  45. Steffen Stein, Arne Hamann, Rolf Ernst
    Real-time Management in Emergent Systems. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2006, pp:104-111 [Conf]
  46. Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
    System level design and debug of high-performance embedded media systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:461- [Conf]
  47. Rolf Ernst, Wei Ye
    Embedded program timing analysis based on path clustering and architecture classification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:598-604 [Conf]
  48. Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner
    Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:96-100 [Conf]
  49. Dirk Herrmann, Rolf Ernst
    Improved interconnect sharing by identity operation insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:489-493 [Conf]
  50. Bren Mochocki, Razvan Racu, Rolf Ernst
    Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:446-449 [Conf]
  51. Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState - an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:558-565 [Conf]
  52. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele
    Representation of process mode correlation for scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:54-61 [Conf]
  53. Rolf Ernst, P. Nowottnick
    Fault Tolerant VLSI Design with Functional Block Redundancy. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:432-436 [Conf]
  54. Ulrich Holtmann, Rolf Ernst
    Speculative Computation for Coprocessor Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:126-131 [Conf]
  55. W. Ye, Rolf Ernst, Thomas Benner, Jörg Henkel
    Fast Timing Analysis for Hardware-Software Co-Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:452-457 [Conf]
  56. Peter Lüders, Rolf Ernst
    The Dynamic Screen - Beyond the Limits of Traditional Graphic User Interfaces. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1994, pp:109-114 [Conf]
  57. Kai Richter, Dirk Ziegenbein, Marek Jersak, Rolf Ernst
    Bottom-Up Performance Analysis of HW/SW Platforms. [Citation Graph (0, 0)][DBLP]
    DIPES, 2002, pp:173-183 [Conf]
  58. Peter Lüders, Rolf Ernst
    Automatic Display Layout in Window Oriented User Interfaces. [Citation Graph (0, 0)][DBLP]
    Interfaces in Industrial Systems for Production Engineering, 1993, pp:27-41 [Conf]
  59. Stefan Stille, Shailey Minocha, Rolf Ernst
    An Adaptive Window Management System. [Citation Graph (0, 0)][DBLP]
    INTERACT, 1997, pp:67-68 [Conf]
  60. Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Ernst
    A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:137-142 [Conf]
  61. Jörg Henkel, Rolf Ernst
    A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:116-121 [Conf]
  62. Fabian Wolf, Rolf Ernst
    Intervals in Software Execution Cost Analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:130-136 [Conf]
  63. Wael Adi, Rolf Ernst, Bassel Soudan, Abdulrahman Hanoun
    VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:24-32 [Conf]
  64. R. Ernst, S. Sutarwala, J.-Y. Jou
    TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:937- [Conf]
  65. Dirk Ziegenbein, Fabian Wolf, Kai Richter, Marek Jersak, Rolf Ernst
    Interval-Based Analysis of Software Processes. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:94-101 [Conf]
  66. Jan Staschulat, Rolf Ernst
    Scalable precision cache analysis for preemptive scheduling. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:157-165 [Conf]
  67. Achim Österling, Rolf Ernst
    Process Versions in Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:94-99 [Conf]
  68. Razvan Racu, Rolf Ernst
    Scheduling Anomaly Detection and Optimization for Distributed Systems with Preemptive Task-Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:325-334 [Conf]
  69. Razvan Racu, Marek Jersak, Rolf Ernst
    Applying Sensitivity Analysis in Real-Time Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2005, pp:160-169 [Conf]
  70. Arne Hamann, Marek Jersak, Kai Richter, Rolf Ernst
    Design Space Exploration and System Optimization with SymTA/S-- Symbolic Timing Analysis for Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:469-478 [Conf]
  71. Kai Richter, Razvan Racu, Rolf Ernst
    Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:236-245 [Conf]
  72. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
    Flexibility/Cost-Tradeoffs of Platform-Based Systems. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:38-56 [Conf]
  73. Kai Richter, Marek Jersak, Rolf Ernst
    A Formal Approach to MpSoC Performance Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:60-67 [Journal]
  74. Rolf Ernst
    Codesign of Embedded Systems: Status and Trends. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:2, pp:45-54 [Journal]
  75. Rolf Ernst, Jayaram Bhasker
    Simulation-Based Verification for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1991, v:8, n:1, pp:14-20 [Journal]
  76. Rolf Ernst, Jörg Henkel, Thomas Benner
    Hardware-Software Cosynthesis for Microcontrollers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:64-75 [Journal]
  77. Peter Lüders, Rolf Ernst
    Das Automatisierte Bildschirmlayout. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1995, v:10, n:1, pp:1-13 [Journal]
  78. Rolf Ernst
    Putting It All Together. [Citation Graph (0, 0)][DBLP]
    ACM Queue, 2003, v:1, n:2, pp:- [Journal]
  79. Arne Hamann, Marek Jersak, Kai Richter, Rolf Ernst
    A framework for modular analysis and exploration of heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2006, v:33, n:1-3, pp:101-137 [Journal]
  80. Peter Lüders, Rolf Ernst, Stefan Stille
    An Approach to Automatic Display Layout Using Combinatorial Optimization Algorithms. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1995, v:25, n:11, pp:1183-1202 [Journal]
  81. Marek Jersak, Kai Richter, Rolf Ernst
    Interval-based analysis in embedded system design. [Citation Graph (0, 0)][DBLP]
    Mathematics and Computers in Simulation, 2004, v:66, n:2-3, pp:231-242 [Journal]
  82. Razvan Racu, Arne Hamann, Rolf Ernst, Kai Richter
    Automotive Software Integration. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:545-550 [Conf]
  83. Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst
    FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:916-921 [Conf]
  84. Simon Schliecker, Steffen Stein, Rolf Ernst
    Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:273-278 [Conf]
  85. Arne Hamann, Rolf Ernst
    Efficient priority optimization in complex distributed embedded systems through search space adaptation. [Citation Graph (0, 0)][DBLP]
    GECCO, 2007, pp:1517- [Conf]
  86. Peter Lüders, Rolf Ernst
    Research report: improving browsing in information by the automatic display layout. [Citation Graph (0, 0)][DBLP]
    INFOVIS, 1995, pp:26-35 [Conf]
  87. Rafik Henia, Razvan Racu, Rolf Ernst
    Improved Output Jitter Calculation for Compositional Performance Analysis of Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  88. Razvan Racu, Arne Hamann, Rolf Ernst
    Automotive System Optimization using Sensitivity Analysis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:57-70 [Conf]
  89. Jan Staschulat, Rolf Ernst
    Scalable precision cache analysis for real-time software. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
  90. Ulrich Holtmann, Rolf Ernst
    Experiments with low-level speculative computation based on multiple branch prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:262-267 [Journal]
  91. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]
  92. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
    SPI - a system model for heterogeneously specified embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:379-389 [Journal]

  93. Distributed Performance Control in Organic Embedded Systems. [Citation Graph (, )][DBLP]

  94. Combined approach to system level performance analysis of embedded systems. [Citation Graph (, )][DBLP]

  95. Automotive networks: are new busses and gateways the answer or just another challenge? [Citation Graph (, )][DBLP]

  96. Improved response time analysis of tasks scheduled under preemptive Round-Robin. [Citation Graph (, )][DBLP]

  97. Providing accurate event models for the analysis of heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  98. Reliable performance analysis of a multicore multithreaded system-on-chip. [Citation Graph (, )][DBLP]

  99. A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  100. FlexFilm - an Image Processor for Digital Film Processing. [Citation Graph (, )][DBLP]

  101. Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures. [Citation Graph (, )][DBLP]

  102. Formal Methods in System and MpSoC Performance Analysis and Optimisation. [Citation Graph (, )][DBLP]

  103. Modeling Event Stream Hierarchies with Hierarchical Event Models. [Citation Graph (, )][DBLP]

  104. Register synthesis for speculative computation. [Citation Graph (, )][DBLP]

  105. Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. [Citation Graph (, )][DBLP]

  106. A link arbitration scheme for quality of service in a latency-optimized network-on-chip. [Citation Graph (, )][DBLP]

  107. Panel session - Multicore, will Startups drive innovation? [Citation Graph (, )][DBLP]

  108. Learning early-stage platform dimensioning from late-stage timing verification. [Citation Graph (, )][DBLP]

  109. Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. [Citation Graph (, )][DBLP]

  110. Application-specific memory performance of a heterogeneous reconfigurable architecture. [Citation Graph (, )][DBLP]

  111. Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks. [Citation Graph (, )][DBLP]

  112. Bounding the shared resource load for the performance analysis of multiprocessor systems. [Citation Graph (, )][DBLP]

  113. A software update service with self-protection capabilities. [Citation Graph (, )][DBLP]

  114. A Formal Approach to Multi-Dimensional Sensitivity Analysis of Embedded Real-Time Systems. [Citation Graph (, )][DBLP]

  115. Worst case timing analysis of input dependent data cache behavior. [Citation Graph (, )][DBLP]

  116. Construction and Deconstruction of Hierarchical Event Streams with Multiple Hierarchical Layers. [Citation Graph (, )][DBLP]

  117. A Polynomial-Time Algorithm for Computing Response Time Bounds in Static Priority Scheduling Employing Multi-linear Workload Bounds. [Citation Graph (, )][DBLP]

  118. Influence of different system abstractions on the performance analysis of distributed real-time systems. [Citation Graph (, )][DBLP]

  119. Methods for multi-dimensional robustness optimization in complex embedded systems. [Citation Graph (, )][DBLP]

  120. Scalable performance scheduling for hardware-software cosynthesis. [Citation Graph (, )][DBLP]

  121. Simulation based verification of register-transfer level behavioral synthesis tools. [Citation Graph (, )][DBLP]

  122. A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. [Citation Graph (, )][DBLP]

  123. Real-Time Property Verification in Organic Computing Systems. [Citation Graph (, )][DBLP]

  124. Cost-Efficient Worst-Case Execution Time Analysis in Industrial Practice. [Citation Graph (, )][DBLP]

  125. Reliability Analysis of Single Bus Communication with Real-Time Requirements. [Citation Graph (, )][DBLP]

  126. Probabilistic Network Loads with Dependencies and the Effect on Queue Sojourn Times. [Citation Graph (, )][DBLP]

  127. Multi-dimensional Robustness Optimization in Heterogeneous Distributed Embedded Systems. [Citation Graph (, )][DBLP]

  128. Scenario Aware Analysis for Complex Event Models and Distributed Systems. [Citation Graph (, )][DBLP]

  129. Analysis of Memory Latencies in Multi-Processor Systems. [Citation Graph (, )][DBLP]

  130. A Framework for the Busy Time Calculation of Multiple Correlated Events. [Citation Graph (, )][DBLP]

  131. Modelling and designing reliable on-chip-communication devices in MPSoCs with real-time requirements. [Citation Graph (, )][DBLP]

  132. Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks. [Citation Graph (, )][DBLP]

  133. Dependency-aware stochastic analysis of chained execution times. [Citation Graph (, )][DBLP]

  134. Early Architecture Exploration with SymTA/S. [Citation Graph (, )][DBLP]

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