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Sudeep Pasricha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudeep Pasricha, Mohamed Ben-Romdhane
    Using TLM for Exploring Bus-based SoC Communication Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:79-85 [Conf]
  2. Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
    Automated throughput-driven synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:495-498 [Conf]
  3. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Constraint-driven bus matrix synthesis for MPSoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:30-35 [Conf]
  4. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Fast exploration of bus-based on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:242-247 [Conf]
  5. Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt
    System-level power-performance trade-offs in bus matrix communication architecture synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:300-305 [Conf]
  6. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Extending the transaction level modeling approach for fast communication architecture exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:113-118 [Conf]
  7. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:565-570 [Conf]
  8. Sudeep Pasricha, Nikil D. Dutt
    COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:700-705 [Conf]
  9. Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil Dutt, Qiang Zhu
    Formal performance evaluation of AMBA-based system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:311-320 [Conf]
  10. Sudeep Pasricha, Shivajit Mohapatra, Manev Luthra, Nikil D. Dutt, Nalini Venkatasubramanian
    Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:11-17 [Conf]
  11. Sudeep Pasricha, Alexander V. Veidenbaum
    Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:526-531 [Conf]
  12. Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
    Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:8- [Conf]
  13. Sudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian
    Dynamic Backlight Adaptation for Low-Power Handheld Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:398-405 [Journal]
  14. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    FABSYN: floorplan-aware bus architecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:241-253 [Journal]

  15. Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. [Citation Graph (, )][DBLP]


  16. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  17. Methodology for multi-granularity embedded processor power model generation for an ESL design flow. [Citation Graph (, )][DBLP]


  18. Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. [Citation Graph (, )][DBLP]


  19. Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. [Citation Graph (, )][DBLP]


  20. Exploring serial vertical interconnects for 3D ICs. [Citation Graph (, )][DBLP]


  21. Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. [Citation Graph (, )][DBLP]


  22. A framework for memory-aware multimedia application mapping on chip-multiprocessors. [Citation Graph (, )][DBLP]


  23. System level power estimation methodology with H.264 decoder prediction IP case study. [Citation Graph (, )][DBLP]


  24. UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications. [Citation Graph (, )][DBLP]


  25. Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. [Citation Graph (, )][DBLP]


  26. Compiler driven data layout optimization for regular/irregular array access patterns. [Citation Graph (, )][DBLP]


  27. Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. [Citation Graph (, )][DBLP]


  28. Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. [Citation Graph (, )][DBLP]


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