Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. [Citation Graph (, )][DBLP]
Exploring serial vertical interconnects for 3D ICs. [Citation Graph (, )][DBLP]
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. [Citation Graph (, )][DBLP]
A framework for memory-aware multimedia application mapping on chip-multiprocessors. [Citation Graph (, )][DBLP]
System level power estimation methodology with H.264 decoder prediction IP case study. [Citation Graph (, )][DBLP]
UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications. [Citation Graph (, )][DBLP]
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. [Citation Graph (, )][DBLP]
Compiler driven data layout optimization for regular/irregular array access patterns. [Citation Graph (, )][DBLP]
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. [Citation Graph (, )][DBLP]
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. [Citation Graph (, )][DBLP]
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