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Mohamed Ben-Romdhane: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudeep Pasricha, Mohamed Ben-Romdhane
    Using TLM for Exploring Bus-based SoC Communication Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:79-85 [Conf]
  2. Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
    Automated throughput-driven synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:495-498 [Conf]
  3. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Constraint-driven bus matrix synthesis for MPSoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:30-35 [Conf]
  4. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Fast exploration of bus-based on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:242-247 [Conf]
  5. Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane
    System level design: six success stories in search of an industry. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:349-350 [Conf]
  6. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Extending the transaction level modeling approach for fast communication architecture exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:113-118 [Conf]
  7. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:565-570 [Conf]
  8. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    FABSYN: floorplan-aware bus architecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:241-253 [Journal]

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