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N. Ranganathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee
    Software and Hardware Enhancement of Arithmetic Coding. [Citation Graph (1, 9)][DBLP]
    SSDBM, 1988, pp:120-132 [Conf]
  2. Minesh I. Patel, N. Ranganathan
    A VLSI System Architecture For Real-Time Intelligent Decision Making. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:221-230 [Conf]
  3. K. Sitaraman, N. Ranganathan, Abdel Ejnioui
    A VLSI Architecture for Object Recognition Using Tree Matching. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:325-334 [Conf]
  4. Sanjukta Bhanja, N. Ranganathan
    Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:187-192 [Conf]
  5. Ashok K. Murugavel, N. Ranganathan
    A Real Delay Switching Activity Simulator based on Petri net Modeling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:181-186 [Conf]
  6. N. Ranganathan, Ashok K. Murugavel
    A low power scheduler using game theory. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:126-131 [Conf]
  7. Narayanan Vijaykrishnan, N. Ranganathan
    Tuning Branch Predictors to Support Virtual Method Invocation in Java. [Citation Graph (0, 0)][DBLP]
    COOTS, 1999, pp:217-228 [Conf]
  8. Sanjukta Bhanja, N. Ranganathan
    Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:209-214 [Conf]
  9. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:455-460 [Conf]
  10. Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss
    Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1998, pp:531- [Conf]
  11. Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla
    Object-Oriented Architectural Support for a Java Processor. [Citation Graph (0, 0)][DBLP]
    ECOOP, 1998, pp:330-354 [Conf]
  12. Abdel Ejnioui, N. Ranganathan
    Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:176-185 [Conf]
  13. Vamsi Krishna, N. Ranganathan
    A Methodology for High Level Power Estimation and Exploration. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:420-425 [Conf]
  14. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Simultaneous peak and average power minimization during datapath scheduling for DSP processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:215-220 [Conf]
  15. N. Ranganathan, K. B. Doreswamy
    A systolic algorithm and architecture for image thinning. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:138-143 [Conf]
  16. Raju D. Venkataramana, N. Ranganathan
    Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 1999, pp:137-145 [Conf]
  17. Raju D. Venkataramana, N. Ranganathan
    New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 2000, pp:160-167 [Conf]
  18. Raghu Sastry, N. Ranganathan
    A VLSI Architecture for Computer the Tree-to-Tree Distance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:330-339 [Conf]
  19. Sanjukta Bhanja, N. Ranganathan
    Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:388-390 [Conf]
  20. S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri
    A VLSI chip for image compression using variable block size segmentation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:500-505 [Conf]
  21. Abdel Ejnioui, N. Ranganathan
    Systolic algorithms for tree pattern matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:650-702 [Conf]
  22. Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan
    MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:170-173 [Conf]
  23. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:441-443 [Conf]
  24. Hitoshi Oi, N. Ranganathan
    Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:267-272 [Conf]
  25. N. Ranganathan, Ashok K. Murugavel
    A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:276-281 [Conf]
  26. N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer
    SMAC: A Scene Matching Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:184-187 [Conf]
  27. N. Ranganathan, Satish Venugopal
    A VLSI Chip for Template Matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:542-545 [Conf]
  28. N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
    A VLSI array architecture with dynamic frequency clocking. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:137-140 [Conf]
  29. Raghu Sastry, N. Ranganathan
    A Systolic Array for Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:402-405 [Conf]
  30. Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan
    On Software and Hardware Techniques of Data Engineering. [Citation Graph (0, 8)][DBLP]
    ICDE, 1989, pp:208-215 [Conf]
  31. Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan
    Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 1998, pp:649-653 [Conf]
  32. Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
    Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1997, pp:278-281 [Conf]
  33. N. Ranganathan, Satish Venugopal
    An Efficient VLSI Architecture for Template Matching. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:224-231 [Conf]
  34. Ken Hughes, N. Ranganathan
    A Model for Determining Sensor Confidence. [Citation Graph (0, 0)][DBLP]
    ICRA (2), 1993, pp:136-141 [Conf]
  35. Mario Kovac, N. Ranganathan, M. Varanasi
    A Systolic Algorithm and Architecture for Galois Field Arithmetic. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:283-288 [Conf]
  36. N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes
    A Parallel Algorithm and Architecture for Robot Path Planning. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:275-279 [Conf]
  37. Raghu Sastry, N. Ranganathan, Ramesh Jain
    VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:700-704 [Conf]
  38. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:313-316 [Conf]
  39. Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
    Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:323-326 [Conf]
  40. Hitoshi Oi, N. Ranganathan
    Utilization of Cache Area in On-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1999, pp:373-380 [Conf]
  41. Ashok K. Murugavel, N. Ranganathan
    Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:267-270 [Conf]
  42. V. Mahalingam, N. Ranganathan, Justin E. Harlow III
    A novel approach for variation aware power minimization during gate sizing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:174-179 [Conf]
  43. V. Mahalingam, N. Ranganathan
    Variation Aware Timing Based Placement Using Fuzzy Programming. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:327-332 [Conf]
  44. V. Mahalingam, N. Ranganathan
    A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:180-185 [Conf]
  45. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Peak Power Minimization Through Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:121-126 [Conf]
  46. Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna
    Datapath Scheduling using Dynamic Frequency Clocking. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:65-70 [Conf]
  47. N. Ranganathan, Hassan N. Srinidhi
    Effect of Data Compression Hardware on the Performance of a Relational Database Machine. [Citation Graph (0, 0)][DBLP]
    PARBASE, 1990, pp:144-146 [Conf]
  48. Raju D. Venkataramana, N. Ranganathan
    A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. [Citation Graph (0, 0)][DBLP]
    SAC, 1999, pp:541-547 [Conf]
  49. Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee
    A scheme for data compression in supercomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:272-278 [Conf]
  50. S. Henriques, N. Ranganathan
    A parallel architecture for data compression. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:260-266 [Conf]
  51. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
    Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:586-591 [Conf]
  52. Sanjukta Bhanja, N. Ranganathan
    Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:187-192 [Conf]
  53. Abdel Ejnioui, N. Ranganathan
    Design Partitioning on Single-Chip Emulation Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:234-239 [Conf]
  54. Abdel Ejnioui, N. Ranganathan
    Routing on Switch Matrix Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:248-253 [Conf]
  55. Mario Kovac, N. Ranganathan
    ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:291-296 [Conf]
  56. Mario Kovac, N. Ranganathan
    JAGUAR: a high speed VLSI chip for JPEG image compression standard. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:220-224 [Conf]
  57. Mario Kovac, N. Ranganathan, M. Varanasi
    SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:25-30 [Conf]
  58. Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
    Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:230-233 [Conf]
  59. Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
    A tree matching chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:280-285 [Conf]
  60. Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan
    Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:440-0 [Conf]
  61. V. Mahalingam, N. Ranganathan
    An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:393-398 [Conf]
  62. Saraju P. Mohanty, N. Ranganathan
    Energy Efficient Scheduling for Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:446-451 [Conf]
  63. Saraju P. Mohanty, N. Ranganathan
    A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:539-545 [Conf]
  64. Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan
    Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:153-158 [Conf]
  65. Ashok K. Murugavel, N. Ranganathan
    A Real Delay Switching Activity Simulator Based on Petri Net Modeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:181-186 [Conf]
  66. Ashok K. Murugavel, N. Ranganathan
    A Game-Theoretic Approach for Binding in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:452-0 [Conf]
  67. Ashok K. Murugavel, N. Ranganathan
    Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:195-200 [Conf]
  68. Ashok K. Murugavel, N. Ranganathan
    Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:670-0 [Conf]
  69. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Average Power in Digital CMOS Circuits using Least Square Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:215-220 [Conf]
  70. Ashley Rasquinha, N. Ranganathan
    C3L: A Chip for Connected Component Labeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:446-450 [Conf]
  71. Raghu Sastry, N. Ranganathan, Horst Bunke
    Hardware Algorithms for Polygon Matching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:41-44 [Conf]
  72. Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan
    CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:228-233 [Conf]
  73. Narayanan Vijaykrishnan, N. Ranganathan
    SUBGEN: a genetic approach for subcircuit extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:343-345 [Conf]
  74. N. Ranganathan
    A Forum for VLSI Practitioners. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:10, pp:86- [Journal]
  75. N. Ranganathan, Mubarak Shah
    A VLSI architecture for computing scale space. [Citation Graph (0, 0)][DBLP]
    Computer Vision, Graphics, and Image Processing, 1988, v:43, n:2, pp:178-204 [Journal]
  76. N. Ranganathan, Sharad C. Seth
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:5- [Journal]
  77. Ken Hughes, N. Ranganathan
    Modeling Sensor Confidence for Sensor Integration Tasks. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1994, v:8, n:6, pp:1301-1318 [Journal]
  78. N. Ranganathan, Raghu Sastry
    VLSI Architectures for Pattern Matching. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1994, v:8, n:4, pp:815-843 [Journal]
  79. Raghu Sastry, N. Ranganathan
    PMAC: A Polygon Matching Chip. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:367-385 [Journal]
  80. Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan
    Enhancing arithmetic and tree-based coding. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 1989, v:25, n:3, pp:293-305 [Journal]
  81. Raghu Sastry, N. Ranganathan, Ramesh Jain
    VLSI Architectures for High-Speed Range Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1995, v:17, n:9, pp:894-899 [Journal]
  82. Raghu Sastry, N. Ranganathan, Klinton Remedios
    CASM: A VLSI Chip for Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1995, v:17, n:8, pp:824-830 [Journal]
  83. Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan
    Stochastic channel-adaptive rate control for wireless video transmission. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 2004, v:25, n:7, pp:793-806 [Journal]
  84. N. Ranganathan, Raghu Sastry, R. Venkatesan
    SMAC: A VLSI Architecture for Scene Matching. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1998, v:4, n:3, pp:171-180 [Journal]
  85. Raghu Sastry, N. Ranganathan
    A VLSI Architecture for Approximate Tree Matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:3, pp:346-352 [Journal]
  86. Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
    Context-based lossless image coding using EZW framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:4, pp:554-559 [Journal]
  87. Saraju P. Mohanty, N. Ranganathan
    Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:330-353 [Journal]
  88. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    ILP models for simultaneous energy and transient power minimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:186-212 [Journal]
  89. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
    A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:773-796 [Journal]
  90. N. Ranganathan, Minesh I. Patel, R. Sathyamurthy
    An intelligent system for failure detection and control in an autonomous underwater vehicle. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part A, 2001, v:31, n:6, pp:762-767 [Journal]
  91. Sanjukta Bhanja, N. Ranganathan
    Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1360-1370 [Journal]
  92. N. Ranganathan
    Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:1-11 [Journal]
  93. Raghu Sastry, N. Ranganathan, Horst Bunke
    VLSI architectures for polygon recognition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:398-407 [Journal]
  94. Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya
    MARVLE: a VLSI chip for data compression using tree-based codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:203-214 [Journal]
  95. Mario Kovac, N. Ranganathan, M. Varanasi
    SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:22-30 [Journal]
  96. Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
    A tree-matching chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:277-280 [Journal]
  97. Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
    Computation of lower bounds for switching activity using decision theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:125-129 [Journal]
  98. Abdel Ejnioui, N. Ranganathan
    A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:407-410 [Journal]
  99. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Least-square estimation of average power in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:55-58 [Journal]
  100. Sanjukta Bhanja, N. Ranganathan
    Switching activity estimation of VLSI circuits using Bayesian networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:558-567 [Journal]
  101. Ashok K. Murugavel, N. Ranganathan
    A game theoretic approach for power optimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1031-1043 [Journal]
  102. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:921-927 [Journal]
  103. Abdel Ejnioui, N. Ranganathan
    Routing on field-programmable switch matrices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:283-287 [Journal]
  104. Abdel Ejnioui, N. Ranganathan
    Multiterminal net routing for partial crossbar-based multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:71-78 [Journal]

  105. Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. [Citation Graph (, )][DBLP]


  106. Adaptive VBR video traffic management for higher utilization of ATM networks. [Citation Graph (, )][DBLP]


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