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Margarida F. Jacome: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Helvio P. Peixoto, Margarida F. Jacome
    Algorithm and architecture-level design space exploration using hierarchical data flows. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:272-282 [Conf]
  2. Jeffry T. Russell, Margarida F. Jacome
    Scenario-based software characterization as a contingency to traditional program profiling. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:170-177 [Conf]
  3. Cagdas Akturan, Margarida F. Jacome
    RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:67-72 [Conf]
  4. R. Anand, Margarida F. Jacome, Gustavo de Veciana
    Heuristic tradeoffs between latency and energy consumption in register assignment. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:115-119 [Conf]
  5. Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan
    Resource constrained dataflow retiming heuristics for VLIW ASIPs. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:12-16 [Conf]
  6. Margarida F. Jacome, Stephen W. Director
    Design Process Management for CAD Frameworks. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:500-505 [Conf]
  7. Margarida F. Jacome, Chen He, Gustavo de Veciana, Stephen Bijansky
    Defect tolerant probabilistic design paradigm for nanotechnologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:596-601 [Conf]
  8. Margarida F. Jacome, Gustavo de Veciana, Satish Pillai
    Clustered VLIW Architectures with Predicated Switching. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:696-701 [Conf]
  9. Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana
    High-Quality Operation Binding for Clustered VLIW Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:702-707 [Conf]
  10. Anand Ramachandran, Margarida F. Jacome
    Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:137-142 [Conf]
  11. Jeffry T. Russell, Margarida F. Jacome
    Architecture-level performance evaluation of component-based embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:396-401 [Conf]
  12. Gustavo de Veciana, Margarida F. Jacome, J.-H. Guo
    Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:251-256 [Conf]
  13. Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian
    High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:270-273 [Conf]
  14. Chen He, Margarida F. Jacome
    RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1179-1184 [Conf]
  15. Margarida F. Jacome, Helvio P. Peixoto, Ander Royo, Juan Carlos López
    The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:676-683 [Conf]
  16. Satish Pillai, Margarida F. Jacome
    Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10422-10427 [Conf]
  17. Pedro Merino, Margarida F. Jacome, Juan Carlos López
    A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:324-325 [Conf]
  18. Pedro Merino, Juan Carlos López, Margarida F. Jacome
    A Hardwar Operating System for Dynamic Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:431-435 [Conf]
  19. Helvio P. Peixoto, Margarida F. Jacome
    A new technique for estimating lower bounds on latency for high level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:129-132 [Conf]
  20. Cagdas Akturan, Margarida F. Jacome
    CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:112-118 [Conf]
  21. Margarida F. Jacome, Stephen W. Director
    A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:516-521 [Conf]
  22. Margarida F. Jacome, Gustavo de Veciana
    Lower bound on latency for VLIW ASIP datapaths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:261-269 [Conf]
  23. Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii
    Exploring Performance Tradeoffs for Clustered VLIW ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:504-510 [Conf]
  24. Satish Pillai, Margarida F. Jacome
    Symbolic Binding for Clustered VLIW ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:437-444 [Conf]
  25. Jeffry T. Russell, Margarida F. Jacome
    Embedded Architect: A Tool for Early Performance Evaluation of Embedded Software. [Citation Graph (0, 0)][DBLP]
    ICSE, 2003, pp:824-825 [Conf]
  26. Cagdas Akturan, Margarida F. Jacome
    FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:34-40 [Conf]
  27. Chen He, Marcello Lajolo, Margarida F. Jacome
    A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:401-408 [Conf]
  28. Hugo A. Andrade, Margarida F. Jacome
    The Common Hardware and Software Object Model: CHSOM. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  29. Helvio P. Peixoto, Margarida F. Jacome, Ander Royo
    A Tight Area Upper Bound for Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:280-0 [Conf]
  30. Margarida F. Jacome, Viktor S. Lapinskii
    NREC: Risk Assessment and Planning of Complex Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:42-49 [Journal]
  31. Margarida F. Jacome, Helvio P. Peixoto
    A Survey of Digital Design Reuse. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:98-107 [Journal]
  32. Margarida F. Jacome, Gustavo de Veciana
    Design Challenges for New Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:40-50 [Journal]
  33. Chen He, Margarida F. Jacome, Gustavo de Veciana
    A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:316-326 [Journal]
  34. Cagdas Akturan, Margarida F. Jacome
    RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1395-1415 [Journal]
  35. Margarida F. Jacome, Stephen W. Director
    A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1197-1210 [Journal]
  36. Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana
    Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:889-903 [Journal]
  37. Satish Pillai, Margarida F. Jacome
    Predicated switching - optimizing speculation on EPIC machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:318-335 [Journal]
  38. Anand Ramachandran, Margarida F. Jacome
    Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:832-848 [Journal]
  39. Margarida F. Jacome, Francky Catthoor
    Special issue on power-aware embedded computing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:251-254 [Journal]
  40. Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana
    Cluster assignment for high-performance embedded VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:430-454 [Journal]

  41. Global Optimization of Compositional Systems. [Citation Graph (, )][DBLP]


  42. Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures. [Citation Graph (, )][DBLP]


  43. An RFID-Based Platform Supporting Context-Aware Computing in Complex Spaces. [Citation Graph (, )][DBLP]


  44. Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units. [Citation Graph (, )][DBLP]


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