The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Laura Pozzi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
    Automatic Instruction Set Extension and Utilization for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:108-0 [Conf]
  2. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:339-351 [Conf]
  3. Laura Pozzi, Paolo Ienne
    Exploiting pipelining to relax register-file port constraints of instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:2-10 [Conf]
  4. Paolo Bonzini, Laura Pozzi
    Code transformation strategies for extensible embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:242-252 [Conf]
  5. Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne
    Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:243-248 [Conf]
  6. Kubilay Atasu, Laura Pozzi, Paolo Ienne
    Automatic application-specific instruction-set extensions under microarchitectural constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:256-261 [Conf]
  7. Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt
    Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:729-734 [Conf]
  8. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:948-953 [Conf]
  9. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    A DAG-Based Design Approach for Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:778-779 [Conf]
  10. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1246-1251 [Conf]
  11. Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Automatic identification of application-specific functional units with architecturally visible storage. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:212-217 [Conf]
  12. Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
    Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:218-223 [Conf]
  13. Laura Pozzi, Miljan Vuletic, Paolo Ienne
    Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1138- [Conf]
  14. Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
    Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:748- [Conf]
  15. Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami
    Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:85-93 [Conf]
  16. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:24-33 [Conf]
  17. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:218- [Conf]
  18. Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami
    Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:258- [Conf]
  19. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:596-605 [Conf]
  20. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:50-57 [Conf]
  21. Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
    Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:17-32 [Conf]
  22. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:651-656 [Conf]
  23. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Seamless Hardware-Software Integration in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:102-113 [Journal]
  24. Kubilay Atasu, Laura Pozzi, Paolo Ienne
    Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:6, pp:411-428 [Journal]
  25. Laura Pozzi, Kubilay Atasu, Paolo Ienne
    Exact and approximate algorithms for the extension of embedded processor instruction sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1209-1229 [Journal]
  26. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal]
  27. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:910-915 [Journal]
  28. André DeHon, Yury Markovskiy, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
    Stream computations organized for reconfigurable execution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:334-354 [Journal]
  29. Paolo Bonzini, Laura Pozzi
    Polynomial-time subgraph enumeration for automated instruction set extension. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1331-1336 [Conf]
  30. Laura Pozzi, Pierre G. Paulin
    A future of customizable processors: are we there yet? [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1224-1225 [Conf]
  31. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
  32. Paolo Bonzini, Dilek Harmanci, Laura Pozzi
    A Study of Energy Saving in Customizable Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:304-312 [Conf]
  33. Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  34. A Retargetable Framework for Automated Discovery of Custom Instructions. [Citation Graph (, )][DBLP]


  35. Compiling custom instructions onto expression-grained reconfigurable architectures. [Citation Graph (, )][DBLP]


  36. Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. [Citation Graph (, )][DBLP]


  37. Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.006secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002