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Giovanni De Micheli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
    Automatic Instruction Set Extension and Utilization for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:108-0 [Conf]
  2. Terry Tao Ye, Giovanni De Micheli
    Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:97-107 [Conf]
  3. Srinivasan Murali, Luca Benini, Giovanni De Micheli
    Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:27-32 [Conf]
  4. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    Mapping and configuration methods for multi-use-case networks on chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:146-151 [Conf]
  5. Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli
    Performance driven reliable link design for networks on chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:749-754 [Conf]
  6. Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli
    Enhanced pClustering and Its Applications to Gene Expression Data. [Citation Graph (0, 0)][DBLP]
    BIBE, 2004, pp:275-282 [Conf]
  7. Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini
    Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images. [Citation Graph (0, 0)][DBLP]
    CBMS, 2006, pp:413-418 [Conf]
  8. Igino Folcarelli, Alex Susu, Ties Kluter, Giovanni De Micheli, Andrea Acquaviva
    An opportunistic reconfiguration strategy for environmentally powered devices. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:171-176 [Conf]
  9. Rajesh K. Gupta, Giovanni De Micheli
    Constrained software generation for hardware-software systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:56-63 [Conf]
  10. Claudionor José Nunes Coelho Jr., Jerry Chih-Yuan Yang, Vincent John Mooney III, Giovanni De Micheli
    Redesigning hardware-software systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:116-123 [Conf]
  11. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Low-power task scheduling for multiple devices. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:39-43 [Conf]
  12. Yung-Hsiang Lu, Tajana Simunic, Giovanni De Micheli
    Software controlled power management. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:157-161 [Conf]
  13. Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:130-135 [Conf]
  14. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias
    A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:618-623 [Conf]
  15. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Computational Kernels and their Application to Sequential Power Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:764-769 [Conf]
  16. Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:247-252 [Conf]
  17. David C. Ku, Giovanni De Micheli
    Relative Scheduling Under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:59-64 [Conf]
  18. Maurizio Damiani, Giovanni De Micheli
    Recurrence Equations and the Optimization of Synchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:556-561 [Conf]
  19. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
    Optimization of Combinational Logic Circuits Based on Compatible Gates. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:631-636 [Conf]
  20. Silvia Ercolani, Giovanni De Micheli
    Technology Mapping for Electrically Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:234-239 [Conf]
  21. Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:225-230 [Conf]
  22. David C. Ku, Dave Filo, Giovanni De Micheli
    Control Optimization Based on Resynchronization of Operations. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:366-371 [Conf]
  23. Giovanni De Micheli
    Reliable communication in systems on chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:77- [Conf]
  24. Giovanni De Micheli, David C. Ku
    HERCULES - a System for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:483-488 [Conf]
  25. Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
    A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:845-848 [Conf]
  26. Srinivasan Murali, Giovanni De Micheli
    SUNMAP: a tool for automatic topology selection and generation for NoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:914-919 [Conf]
  27. Giuseppe A. Paleologo, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Policy Optimization for Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:182-187 [Conf]
  28. Armita Peymandoust, Giovanni De Micheli
    Using Symbolic Algebra in Algorithmic Level DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:277-282 [Conf]
  29. Armita Peymandoust, Giovanni De Micheli, Tajana Simunic
    Complex library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:325-330 [Conf]
  30. Polly Siegel, Giovanni De Micheli, David L. Dill
    Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:61-67 [Conf]
  31. Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli
    Dynamic Voltage Scaling and Power Management for Portable Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:524-529 [Conf]
  32. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Cycle-Accurate Simulation of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:867-872 [Conf]
  33. James Smith, Giovanni De Micheli
    Automated Composition of Hardware Components. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:14-19 [Conf]
  34. Terry Tao Ye, Giovanni De Micheli, Luca Benini
    Analysis of power consumption on switch fabrics in network routers. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:524-529 [Conf]
  35. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:163-167 [Conf]
  36. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
    Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:861-0 [Conf]
  37. Davide Bertozzi, Luca Benini, Giovanni De Micheli
    Low Power Error Resilient Encoding for On-Chip Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:102-109 [Conf]
  38. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
    Characterization-Free Behavioral Power Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:767-773 [Conf]
  39. Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic Power Management for non-stationary service requests. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:77-81 [Conf]
  40. Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A Complete Network-On-Chip Emulation Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:246-251 [Conf]
  41. Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli
    ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:884-889 [Conf]
  42. Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini
    Quantitative Comparison of Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:20-26 [Conf]
  43. G. Martin, Ralf Seepold, Ting Zhang, Luca Benini, Giovanni De Micheli
    Component selection and matching for IP-based design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:40-46 [Conf]
  44. Giovanni De Micheli
    Hardware Synthesis from C/C++ Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:382-383 [Conf]
  45. Giovanni De Micheli, Luca Benini
    Networks on Chip: A New Paradigm for Systems on Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:418-419 [Conf]
  46. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    A methodology for mapping multiple use-cases onto networks on chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:118-123 [Conf]
  47. Srinivasan Murali, Giovanni De Micheli
    Bandwidth-Constrained Mapping of Cores onto NoC Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:896-903 [Conf]
  48. Srinivasan Murali, Giovanni De Micheli
    An Application-Specific Design Methodology for STbus Crossbar Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1176-1181 [Conf]
  49. Armita Peymandoust, Tajana Simunic, Giovanni De Micheli
    Low Power Embedded Software Optimization Using Symbolic Algebra. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1052-1058 [Conf]
  50. Luc Séméria, Koichi Sato, Giovanni De Micheli
    Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:312-319 [Conf]
  51. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Dynamic Power Management of Laptop Hard Disk. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:736- [Conf]
  52. James Smith, Giovanni De Micheli
    Polynomial Methods for Allocating Complex Components. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:217-222 [Conf]
  53. Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
    ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1188-1193 [Conf]
  54. Terry Tao Ye, Luca Benini, Giovanni De Micheli
    Packetized On-Chip Interconnect Communication Analysis for MPSoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10344-10349 [Conf]
  55. Kresimir Mihic, Tajana Simunic, Giovanni De Micheli
    Reliability and Power Management of Integrated Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:5-11 [Conf]
  56. Sungroh Yoon, Giovanni De Micheli
    Prediction of regulatory modules comprising microRNAs and target genes. [Citation Graph (0, 0)][DBLP]
    ECCB/JBI, 2005, pp:100- [Conf]
  57. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
    Scheduling with Environmental Constraints based on Automata Representations. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:495-501 [Conf]
  58. Diego C. Ruspini, Oussama Khatib, Giovanni De Micheli
    Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10162-10167 [Conf]
  59. Marco Platzner, Giovanni De Micheli
    Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:69-78 [Conf]
  60. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
    Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:8-12 [Conf]
  61. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Timed Supersetting and the Synthesis of Telescopic Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:331-337 [Conf]
  62. Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
    Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf]
  63. Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli
    A simulation methodology for reliability analysis in multi-core SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:95-99 [Conf]
  64. Yung-Hsiang Lu, Giovanni De Micheli
    Adaptive Hard Disk Power Management on Personal Computers. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:50-0 [Conf]
  65. Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias
    Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:311-316 [Conf]
  66. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic power management of electronic systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:696-702 [Conf]
  67. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Fast power estimation for deterministic input streams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:494-501 [Conf]
  68. Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
    Modeling hierarchical combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:612-617 [Conf]
  69. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Dynamic power management using adaptive learning tree. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:274-279 [Conf]
  70. Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:175-181 [Conf]
  71. Maurizio Damiani, Giovanni De Micheli
    Observability Don't Care Sets and Boolean Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:502-505 [Conf]
  72. Rajesh K. Gupta, Giovanni De Micheli
    Partitioning of Functional Models of Synchronous Digital Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:216-219 [Conf]
  73. Shin-ichi Minato, Giovanni De Micheli
    Finding all simple disjunctive decompositions using irredundant sum-of-products forms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:111-117 [Conf]
  74. Vincent John Mooney III, Giovanni De Micheli
    Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:605-612 [Conf]
  75. Armita Peymandoust, Giovanni De Micheli
    Symbolic Algebra and Timing Driven Data-flow Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:300-305 [Conf]
  76. Luc Séméria, Giovanni De Micheli
    SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:340-346 [Conf]
  77. Polly Siegel, Giovanni De Micheli
    Decomposition methods for library binding of speed-independent asynchronous designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:558-565 [Conf]
  78. James Smith, Giovanni De Micheli
    Polynomial methods for component matching and verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:678-685 [Conf]
  79. Patrick Vuillod, Luca Benini, Giovanni De Micheli
    Generalized matching from theory to application. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:13-20 [Conf]
  80. Terry Tao Ye, Giovanni De Micheli
    Data Path Placement with Regularity. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:264-270 [Conf]
  81. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  82. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Distributed EDA Tool Integration: The PPP Paradigm. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:448-453 [Conf]
  83. Jérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli
    A Synthesis Framework Based on Trace and Automata Theory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:291-294 [Conf]
  84. Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A novel approach for network on chip emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2365-2368 [Conf]
  85. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    Self-calibrating networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2361-2364 [Conf]
  86. Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli
    Physical synthesis for ASIC datapath circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:365-368 [Conf]
  87. Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini
    Mining Gene Sets for Measuring Similarities. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:227-232 [Conf]
  88. Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli
    Efficient switching activity computation during high-level synthesis of control-dominated designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:127-132 [Conf]
  89. Luca Benini, Giovanni De Micheli
    Transformation and synthesis of FSMs for low-power gated-clock implementation. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:21-26 [Conf]
  90. Luca Benini, Giovanni De Micheli
    System-level power optimization: techniques and tools. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:288-293 [Conf]
  91. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    System-level power optimization of special purpose applications: the beach solution. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:24-29 [Conf]
  92. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level current waveform simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:109-112 [Conf]
  93. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Automatic source code specialization for energy reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:80-83 [Conf]
  94. Eui-Young Chung, Giovanni De Micheli, Luca Benini
    Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:42-47 [Conf]
  95. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Operating-system directed power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:37-42 [Conf]
  96. Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari
    Do our low-power tools have enough horse power? (panel session) (title only). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:149- [Conf]
  97. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:212-217 [Conf]
  98. Tajana Simunic, Haris Vikalo, Peter W. Glynn, Giovanni De Micheli
    Energy efficient design of portable wireless systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:49-54 [Conf]
  99. Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Clock skew optimization for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:265-270 [Conf]
  100. Patrick Vuillod, Luca Benini, Giovanni De Micheli
    Re-mapping for low power under tight timing constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:287-292 [Conf]
  101. Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm
    An Adaptive Low-Power Transmission Scheme for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:92-100 [Conf]
  102. Luca Benini, Giovanni De Micheli
    Powering networks on chips. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:33-38 [Conf]
  103. Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:57-0 [Conf]
  104. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Source code transformation based on software cost analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:153-158 [Conf]
  105. Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini
    Requester-Aware Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:18-24 [Conf]
  106. Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli
    Cache-efficient memory layout of aggregate data structures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:101-106 [Conf]
  107. Tajana Simunic, Giovanni De Micheli, Luca Benini
    Event-Driven Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:18-23 [Conf]
  108. Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans
    Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:193-199 [Conf]
  109. Giovanni De Micheli
    Robust System Design with Uncertain Information. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:283-0 [Conf]
  110. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Dynamic power management for portable systems. [Citation Graph (0, 0)][DBLP]
    MOBICOM, 2000, pp:11-19 [Conf]
  111. Wajahat Qadeer, Tajana Simunic Rosing, John Ankcorn, Venky Krishnan, Giovanni De Micheli
    Heterogeneous Wireless Network Management. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:86-100 [Conf]
  112. Nicolas Genko, David Atienza, Giovanni De Micheli
    Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:753-760 [Conf]
  113. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
    Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:107-116 [Conf]
  114. Giovanni De Micheli
    Nanoelectronics: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:658- [Conf]
  115. Tajana Simunic, Kresimir Mihic, Giovanni De Micheli
    Optimization of Reliability and Power Consumption in Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:237-246 [Conf]
  116. Abhishek Garg, Ioannis Xenarios, Luis Mendoza, Giovanni De Micheli
    An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments. [Citation Graph (0, 0)][DBLP]
    RECOMB, 2007, pp:62-76 [Conf]
  117. Giovanni De Micheli
    High-Level Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 1993, v:37, n:, pp:207-283 [Journal]
  118. Luca Benini, Giovanni De Micheli
    Networks on Chips: A New SoC Paradigm. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:1, pp:70-78 [Journal]
  119. Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Program Implementation Schemes for Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:1, pp:48-55 [Journal]
  120. Luca Benini, Polly Siegel, Giovanni De Micheli
    Saving Power by Synthesizing Gated Clocks for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:32-41 [Journal]
  121. Yung-Hsiang Lu, Giovanni De Micheli
    Comparing System-Level Power Management Policies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:10-19 [Journal]
  122. André Ivanov, Giovanni De Micheli
    Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:399-403 [Journal]
  123. Rajesh K. Gupta, Giovanni De Micheli
    Hardware-Software Cosynthesis for Digital Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:3, pp:29-41 [Journal]
  124. Giovanni De Micheli
    CASS Brings Publishing to Its DAC Partnership. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:101-102 [Journal]
  125. Giovanni De Micheli
    Guest Editorial: High-Level Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:5, pp:6-7 [Journal]
  126. Giovanni De Micheli, Al Dunlop
    IEEE Council for Electronic Design Automation: A new beginning. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:293-294 [Journal]
  127. Giovanni De Micheli, David C. Ku, Frederic Mailhot, Thomas K. Truong
    The Olympus Synthesis System. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:5, pp:37-53 [Journal]
  128. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli
    Analysis of Error Recovery Schemes for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:434-442 [Journal]
  129. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
    Design, Synthesis, and Test of Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:404-413 [Journal]
  130. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:524-535 [Journal]
  131. Terry Tao Ye, Luca Benini, Giovanni De Micheli
    Packetization and routing analysis of on-chip multiprocessor networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:81-104 [Journal]
  132. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:769-779 [Journal]
  133. Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Yung-Hsiang Lu, Giovanni De Micheli
    Dynamic Power Management for Nonstationary Service Requests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:11, pp:1345-1361 [Journal]
  134. Davide Bertozzi, Luca Benini, Giovanni De Micheli
    Error control schemes for on-chip communication links: the energy-reliability tradeoff. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:818-831 [Journal]
  135. Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli
    Policy optimization for dynamic power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:813-833 [Journal]
  136. Luca Benini, Giovanni De Micheli
    Automatic synthesis of low-power gated-clock finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:630-643 [Journal]
  137. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Synthesis of power-managed sequential components based oncomputational kernel extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1118-1131 [Journal]
  138. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A multilevel engine for fast power simulation of realistic inputstreams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:459-472 [Journal]
  139. Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
    Telescopic units: a new paradigm for performance optimization of VLSI designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:220-232 [Journal]
  140. Luca Benini, Patrick Vuillod, Giovanni De Micheli
    Iterative remapping for logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:948-964 [Journal]
  141. Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli
    Value-sensitive automatic code specialization for embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1051-1067 [Journal]
  142. Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Analysis and synthesis of concurrent digital circuits using control-flow expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:854-876 [Journal]
  143. Maurizio Damiani, Giovanni De Micheli
    Don't care set specifications in combinational and synchronous logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:365-388 [Journal]
  144. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
    Optimization of combinational logic circuits based on compatible gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1316-1327 [Journal]
  145. Rajesh K. Gupta, Giovanni De Micheli
    Specification and analysis of timing constraints for embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:240-256 [Journal]
  146. David C. Ku, Giovanni De Micheli
    Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:696-718 [Journal]
  147. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Dynamic frequency scaling with buffer insertion for mixed workloads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1284-1305 [Journal]
  148. Frederic Mailhot, Giovanni De Micheli
    Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:599-620 [Journal]
  149. Giovanni De Micheli
    Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:597-616 [Journal]
  150. Giovanni De Micheli
    Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:751-765 [Journal]
  151. Giovanni De Micheli
    Synchronous logic synthesis: algorithms for cycle-time minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:63-73 [Journal]
  152. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimal State Assignment for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:269-285 [Journal]
  153. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Correction to "Optimal State Assignment for Finite State Machines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:239-239 [Journal]
  154. Giovanni De Micheli, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:167-180 [Journal]
  155. Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli
    Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:151-167 [Journal]
  156. Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli
    Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:256-256 [Journal]
  157. Armita Peymandoust, Tajana Simunic, Giovanni De Micheli
    Complex instruction and software library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:964-975 [Journal]
  158. Armita Peymandoust, Giovanni De Micheli
    Application of symbolic computer algebra in high-level data-flow synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1154-1165 [Journal]
  159. Luc Séméria, Giovanni De Micheli
    Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:213-233 [Journal]
  160. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Event-driven power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:840-857 [Journal]
  161. Derek C. Wong, Giovanni De Micheli, Michael J. Flynn
    Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:25-46 [Journal]
  162. Sungroh Yoon, Luca Benini, Giovanni De Micheli
    A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:2, pp:358-377 [Journal]
  163. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
    Scheduling and control generation with environmental constraints based on automata representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:166-183 [Journal]
  164. Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli
    Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Comput. Biology Bioinform., 2005, v:2, n:4, pp:339-354 [Journal]
  165. Luca Benini, Giovanni De Micheli
    System-level power optimization: techniques and tools. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:115-192 [Journal]
  166. Luca Benini, Giovanni De Micheli
    Synthesis of low-power selectively-clocked systems from high-level specification. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:311-321 [Journal]
  167. Luca Benini, Giovanni De Micheli
    A survey of Boolean matching techniques for library binding. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:193-226 [Journal]
  168. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:351-375 [Journal]
  169. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
    Regression-based RTL power modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:337-372 [Journal]
  170. Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli
    NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:113-129 [Journal]
  171. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    A robust self-calibrating transmission scheme for on-chip networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:126-139 [Journal]
  172. Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
    Interactive presentation: Improving the fault tolerance of nanometric PLA designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:570-575 [Conf]
  173. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
    Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:121-124 [Conf]
  174. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
    Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:57-64 [Conf]
  175. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  176. Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli
    A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:140-145 [Conf]
  177. Giovanni De Micheli
    Design Technologies for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:149- [Conf]
  178. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  179. Srinivasan Murali, Giovanni De Micheli
    An Application-Specific Design Methodology for STbus Crossbar Generation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  180. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
    Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]
  181. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida
    HW-SW emulation framework for temperature-aware design in MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  182. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]
  183. Tajana Simunic Rosing, Kresimir Mihic, Giovanni De Micheli
    Power and Reliability Management of SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:391-403 [Journal]
  184. Dave Filo, David C. Ku, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Interface optimization for concurrent systems under timing constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:268-281 [Journal]
  185. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level power and current simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:473-488 [Journal]
  186. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    Power optimization of core-based systems by address bus encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:554-562 [Journal]
  187. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch power minimization by selective gate freezing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:287-298 [Journal]
  188. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    A survey of design techniques for system-level dynamic power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:299-316 [Journal]
  189. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:15-28 [Journal]
  190. Luc Séméria, Koichi Sato, Giovanni De Micheli
    Synthesis of hardware models in C with pointers and complex data structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:743-756 [Journal]
  191. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Power-aware operating systems for interactive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:119-134 [Journal]
  192. Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici
    Analysis and Optimization of MPSoC Reliability. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:56-69 [Journal]

  193. A control theory approach for thermal balancing of MPSoC. [Citation Graph (, )][DBLP]


  194. A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. [Citation Graph (, )][DBLP]


  195. Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP]


  196. Synthesis of networks on chips for 3D systems on chips. [Citation Graph (, )][DBLP]


  197. Methods for Designing Reliable Probe Arrays. [Citation Graph (, )][DBLP]


  198. Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. [Citation Graph (, )][DBLP]


  199. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. [Citation Graph (, )][DBLP]


  200. Programmable logic circuits based on ambipolar CNFET. [Citation Graph (, )][DBLP]


  201. NoC topology synthesis for supporting shutdown of voltage islands in SoCs. [Citation Graph (, )][DBLP]


  202. Decoding nanowire arrays fabricated with the multi-spacer patterning technique. [Citation Graph (, )][DBLP]


  203. Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. [Citation Graph (, )][DBLP]


  204. Networks on Chips: from research to products. [Citation Graph (, )][DBLP]


  205. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. [Citation Graph (, )][DBLP]


  206. Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  207. OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  208. Designing Micro/Nano Systems for a Safer and Healthier Tomorrow. [Citation Graph (, )][DBLP]


  209. Adaptive least mean square behavioral power modeling. [Citation Graph (, )][DBLP]


  210. Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP]


  211. Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. [Citation Graph (, )][DBLP]


  212. SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. [Citation Graph (, )][DBLP]


  213. Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]


  214. Panel session - Consolidation, a modern "Moor of Venice" tale. [Citation Graph (, )][DBLP]


  215. Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. [Citation Graph (, )][DBLP]


  216. Panel: First commandment at least, do nothing well! [Citation Graph (, )][DBLP]


  217. Power consumption of logic circuits in ambipolar carbon nanotube technology. [Citation Graph (, )][DBLP]


  218. A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. [Citation Graph (, )][DBLP]


  219. Technology mapping using boolean matching and don't care sets. [Citation Graph (, )][DBLP]


  220. Power distribution paths in 3-D ICS. [Citation Graph (, )][DBLP]


  221. Online convex optimization-based algorithm for thermal management of MPSoCs. [Citation Graph (, )][DBLP]


  222. An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation. [Citation Graph (, )][DBLP]


  223. Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. [Citation Graph (, )][DBLP]


  224. A method for calculating hard QoS guarantees for Networks-on-Chip. [Citation Graph (, )][DBLP]


  225. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]


  226. System-level design technologies for heterogeneous distributed systems. [Citation Graph (, )][DBLP]


  227. Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform. [Citation Graph (, )][DBLP]


  228. Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. [Citation Graph (, )][DBLP]


  229. Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing. [Citation Graph (, )][DBLP]


  230. Synchronous versus asynchronous modeling of gene regulatory networks. [Citation Graph (, )][DBLP]


  231. Modeling stochasticity and robustness in gene regulatory networks. [Citation Graph (, )][DBLP]


  232. Dynamic simulation of regulatory networks using SQUAD. [Citation Graph (, )][DBLP]


  233. Clustering protein environments for function prediction: finding PROSITE motifs in 3D. [Citation Graph (, )][DBLP]


  234. Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow. [Citation Graph (, )][DBLP]


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