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Publications of Author

1. Júlio C. B. de Mattos, Stephan Wong, Luigi Carro
   The Molen FemtoJava Engine. [Citation Graph (0, 0)][DBLP]
   ASAP, 2006, pp:19-22 [Conf]
   
2. Filipa Duarte, Stephan Wong
   Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:229-235 [Conf]
   
3. Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
   A Sum of Absolute Differences Implementation in FPGA Hardware. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 2002, pp:183-188 [Conf]
   
4. Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis
   A Reconfigurable Perfect-Hashing Scheme for Packet Inspection. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:644-647 [Conf]
   
5. Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
   The MOLEN rho-mu-Coded Processor. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:275-285 [Conf]
   
6. Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
   Multimedia Enhanced General-Purpose Processors. [Citation Graph (0, 0)][DBLP]
   IEEE International Conference on Multimedia and Expo (III), 2000, pp:1493-1496 [Conf]
   
7. Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
   General-Purpose Processor Huffman Encoding Extension. [Citation Graph (0, 0)][DBLP]
   ITCC, 2000, pp:158-163 [Conf]
   
8. Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
   Microcoded Reconfigurable Embedded Processors: Current Developments. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:207-223 [Conf]
   
9. Lotfi Mhamdi, Mounir Hamdi, Christopher Kachris, Stephan Wong, Stamatis Vassiliadis
   High-performance switching based on buffered crossbar fabrics. [Citation Graph (0, 0)][DBLP]
   Computer Networks, 2006, v:50, n:13, pp:2271-2285 [Journal]
   
10. Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
    Microcode Processing: Positioning and Directions. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:4, pp:21-31 [Journal]
    
11. Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte
    The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal]
    
12. Mahmood Ahmadi, Stephan Wong
    Modified collision packet classification using counting bloom filter in tuple space. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2007, pp:295-300 [Conf]
    
13. Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis
    Systematic Customization of On-Chip Crossbar Interconnects. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:61-72 [Conf]
    
14. Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
    Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:49-60 [Conf]
    
15. Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
    PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:274-286 [Conf]
    
16. Timo D. Hämäläinen, Stephan Wong, John Glossner, Stamatis Vassiliadis
    Editorial. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:677-678 [Journal]
    
17. 
    Customizing Reconfigurable On-Chip Crossbar Scheduler. [Citation Graph (, )][DBLP]
    
    
18. 
    A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies. [Citation Graph (, )][DBLP]
    
    
19. 
    An Approach for Optimal Bandwidth Allocation in Packet Processing Systems. [Citation Graph (, )][DBLP]
    
    
20. 
    Dynamically reconfigurable register file for a softcore VLIW processor. [Citation Graph (, )][DBLP]
    
    
21. 
    A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC. [Citation Graph (, )][DBLP]
    
    
22. 
    Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. [Citation Graph (, )][DBLP]
    
    
23. 
    A Load/Store Unit for a Memcpy Hardware Accelerator. [Citation Graph (, )][DBLP]
    
    
24. 
    An OCM based shared Memory controller for Virtex 4. [Citation Graph (, )][DBLP]
    
    
25. 
    Collaboration of Reconfigurable Processors in Grid Computing for Multimedia Kernels. [Citation Graph (, )][DBLP]
    
    
26. 
    Coarse Reconfigurable Multimedia Unit Extension. [Citation Graph (, )][DBLP]
    
    
27. 
    Multiple Description Scalable Coding for Video Transmission over Unreliable Networks. [Citation Graph (, )][DBLP]
    
    
28. 
    Introduction to the Future of Reconfigurable Computing and Processor Architectures. [Citation Graph (, )][DBLP]
    
    
29. 
    Weighted Embedded Zero Tree for Scalable Video Compression. [Citation Graph (, )][DBLP]
    
    
30. 
    Optimal Unroll Factor for Reconfigurable Architectures. [Citation Graph (, )][DBLP]
    
    
31. 
    A Memory-Optimized Bloom Filter Using an Additional Hashing Function. [Citation Graph (, )][DBLP]
    
    
32. 
    K-Stage Pipelined Bloom Filter for Packet Classification. [Citation Graph (, )][DBLP]
    
    
33. 
    A Paradigm for Reconfigurable Processing on Grid. [Citation Graph (, )][DBLP]
    
    
34. 
    A Cache Architecture for Counting Bloom Filters. [Citation Graph (, )][DBLP]
    
    
35. 
    A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements. [Citation Graph (, )][DBLP]