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Anupam Chattopadhyay:
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- Md. Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. [Citation Graph (0, 0)][DBLP] ASAP, 2005, pp:154-160 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:280-285 [Conf]
- Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, H. Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Automatic ADL-based operand isolation for embedded processors. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:600-605 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:156-160 [Conf]
- Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. [Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:193-199 [Conf]
- Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Integrated Verification Approach during ADL-Driven Processor Design. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2006, pp:110-118 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Optimization Techniques for ADL-Driven RTL Processor Synthesis. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2005, pp:165-171 [Conf]
- Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte
Power-efficient Instruction Encoding Optimization for Embedded Processors. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:595-600 [Conf]
- Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Design space exploration of partially re-configurable embedded processors. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:319-324 [Conf]
- Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2007, pp:189-194 [Conf]
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. [Citation Graph (, )][DBLP]
Increasing data-bandwidth to instruction-set extensions through register clustering. [Citation Graph (, )][DBLP]
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