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Gerd Ascheid:
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Publications of Author
- Md. Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. [Citation Graph (0, 0)][DBLP] ASAP, 2005, pp:154-160 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:280-285 [Conf]
- Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
A modular simulation framework for architectural exploration of on-chip interconnection networks. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2003, pp:7-12 [Conf]
- Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2005, pp:249-254 [Conf]
- Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
Retargetable code optimization with SIMD instructions. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2006, pp:148-153 [Conf]
- Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Fine-grained application source code profiling for ASIP design. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:329-334 [Conf]
- Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
C Compiler Retargeting Based on Instruction Semantics Models. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:1150-1155 [Conf]
- Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, H. Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Automatic ADL-based operand isolation for embedded processors. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:600-605 [Conf]
- Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
ASIP design and synthesis for non linear filtering in image processing. [Citation Graph (0, 0)][DBLP] DATE Designers' Forum, 2006, pp:233-238 [Conf]
- Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1276-1283 [Conf]
- Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. [Citation Graph (0, 0)][DBLP] DATE Designers' Forum, 2006, pp:221-226 [Conf]
- Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:876-881 [Conf]
- Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A SW performance estimation framework for early system-level-design using fine-grained instrumentation. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:468-473 [Conf]
- Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
An interprocedural code optimization technique for network processors using hardware multi-threading support. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:919-924 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:156-160 [Conf]
- Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1256-1263 [Conf]
- Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Memory Access Micro-Profiling for ASIP Design. [Citation Graph (0, 0)][DBLP] DELTA, 2006, pp:255-262 [Conf]
- Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Integrated Verification Approach during ADL-Driven Processor Design. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2006, pp:110-118 [Conf]
- Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Optimization Techniques for ADL-Driven RTL Processor Synthesis. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2005, pp:165-171 [Conf]
- Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP] SAMOS, 2004, pp:138-148 [Conf]
- Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP] SAMOS, 2004, pp:463-473 [Conf]
- Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Early ISS Integration into Network-on-Chip Designs. [Citation Graph (0, 0)][DBLP] SAMOS, 2004, pp:443-452 [Conf]
- Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. [Citation Graph (0, 0)][DBLP] SCOPES, 2004, pp:33-46 [Conf]
- Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. [Citation Graph (0, 0)][DBLP] SCOPES, 2003, pp:167-181 [Conf]
- Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A fast and generic hybrid simulation approach using C virtual machine. [Citation Graph (0, 0)][DBLP] CASES, 2007, pp:3-12 [Conf]
- Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1349-1354 [Conf]
- Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Design space exploration of partially re-configurable embedded processors. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:319-324 [Conf]
- H. Ishebabi, Gerd Ascheid, Heinrich Meyr, O. Atak, A. Atalar, E. Arikan
An efficient parallelization technique for high throughput FFT-ASIPs. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2007, pp:189-194 [Conf]
- Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
ASIP architecture exploration for efficient IPSec encryption: A case study. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
- Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:43, n:2-3, pp:235-246 [Journal]
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. [Citation Graph (, )][DBLP]
HySim: a fast simulation framework for embedded software development. [Citation Graph (, )][DBLP]
A code-generator generator for multi-output instructions. [Citation Graph (, )][DBLP]
A high-level virtual platform for early MPSoC software development. [Citation Graph (, )][DBLP]
TotalProf: a fast and accurate retargetable source code profiler. [Citation Graph (, )][DBLP]
MAPS: an integrated framework for MPSoC application parallelization. [Citation Graph (, )][DBLP]
Multiprocessor performance estimation using hybrid simulation. [Citation Graph (, )][DBLP]
Retargetable Code Optimization for Predicated Execution. [Citation Graph (, )][DBLP]
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. [Citation Graph (, )][DBLP]
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. [Citation Graph (, )][DBLP]
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. [Citation Graph (, )][DBLP]
Deriving a Joint Interference Detection and Channel Estimation for WB-OFDM from EM-MAP Theory. [Citation Graph (, )][DBLP]
A Concept for Data-Aided Carrier Frequency Estimation at Low Signal-To-Noise Ratios. [Citation Graph (, )][DBLP]
Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. [Citation Graph (, )][DBLP]
Optimal Output Back-Off in OFDM Systems with Nonlinear Power Amplifiers. [Citation Graph (, )][DBLP]
Increasing data-bandwidth to instruction-set extensions through register clustering. [Citation Graph (, )][DBLP]
Task management in MPSoCs: An ASIP approach. [Citation Graph (, )][DBLP]
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). [Citation Graph (, )][DBLP]
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. [Citation Graph (, )][DBLP]
Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. [Citation Graph (, )][DBLP]
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. [Citation Graph (, )][DBLP]
A Bit-Mapping Strategy for Joint Iterative Channel Estimation and Turbo-Decoding. [Citation Graph (, )][DBLP]
Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. [Citation Graph (, )][DBLP]
Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. [Citation Graph (, )][DBLP]
Conversion from Uplink to Downlink Spatio-Temporal Correlation with Cubic Splines. [Citation Graph (, )][DBLP]
Beamforming in Single Frequency Networks with Connection Control. [Citation Graph (, )][DBLP]
Intercell Interference Mitigation with Long-Term Beamforming and Low SINR Feedback Rate in a Multiuser Multicell Unicast Scenario. [Citation Graph (, )][DBLP]
Markov Chain Monte Carlo MIMO Detection for Systems with Imperfect Channel State Information. [Citation Graph (, )][DBLP]
Analysis of Local Quasi-Stationarity Regions in an Urban Macrocell Scenario. [Citation Graph (, )][DBLP]
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. [Citation Graph (, )][DBLP]
Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. [Citation Graph (, )][DBLP]
Multicell Multicast Beamforming with Delayed SNR Feedback. [Citation Graph (, )][DBLP]
Robust MSE-Based Transceiver Optimization in MISO Downlink Cognitive Radio Network. [Citation Graph (, )][DBLP]
Conversion of the spatio-temporal correlation from uplink to downlink in FDD systems. [Citation Graph (, )][DBLP]
Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. [Citation Graph (, )][DBLP]
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. [Citation Graph (, )][DBLP]
Complexity-Efficient Enumeration Techniques for Soft-Input, Soft-Output Sphere Decoding [Citation Graph (, )][DBLP]
Efficient And Portable SDR Waveform Development: The Nucleus Concept [Citation Graph (, )][DBLP]
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding [Citation Graph (, )][DBLP]
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