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Publications of Author

1. Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
   Dynamic-SIMD for lens distortion compensation. [Citation Graph (0, 0)][DBLP]
   ASAP, 2006, pp:261-264 [Conf]
   
2. Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman
   Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP]
   CASES, 2003, pp:63-72 [Conf]
   
3. C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman, Adwin H. Timmer
   Identification and Exploitation of Symmetries in DSP Algorithms. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:602-608 [Conf]
   
4. Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
   A Constraint Driven Approach to Loop Pipelining and Register Binding. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:377-383 [Conf]
   
5. Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
   Constraint satisfaction for storage files with Fifos or stacks during scheduling. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:824- [Conf]
   
6. Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
   Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:254-255 [Conf]
   
7. Qin Zhao, Bart Mesman, Twan Basten
   Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1021-1027 [Conf]
   
8. Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
   Predictable embedding of large data structures in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:388-396 [Conf]
   
9. Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
   Global Analysis of Resource Arbitration for MPSoC. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:71-78 [Conf]
   
10. Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
    Constraint Satisfaction for Relative Location Assignment and Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:384-390 [Conf]
    
11. Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker
    Run-time reconfiguration of communication in SIMD architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
    
12. Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint Analysis for DSP Code Generation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:33-40 [Conf]
    
13. Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk
    Efficient Scheduling of DSP Code on Processors with Distributed Register Files. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:100-106 [Conf]
    
14. Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
    Static resource models of instruction sets. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:159-164 [Conf]
    
15. Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef L. van Meerbergen
    Predictable Embedded Multiprocessor System Design. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:77-91 [Conf]
    
16. Qin Zhao, Bart Mesman, Henk Corporaal
    Limited Address Range Architecture for Reducing Code Size in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:2-16 [Conf]
    
17. Bart Mesman, Qin Zhao, Natalino G. Busá, Katarzyna Leijten-Nowak
    Reconfigurable Instruction-Set Application-Tuning for DSP. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:3, pp:333-352 [Journal]
    
18. Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint analysis for DSP code generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:44-57 [Journal]
    
19. Qin Zhao, Bart Mesman, Twan Basten
    Static resource models for code-size efficient embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:2, pp:219-250 [Journal]
    
20. Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint analysis for code generation: basic techniques and applications in FACTS. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:774-793 [Journal]
    
21. Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
    A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:726-731 [Conf]
    
22. 
    Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration. [Citation Graph (, )][DBLP]
    
    
23. 
    A predictable communication assist. [Citation Graph (, )][DBLP]
    
    
24. 
    Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. [Citation Graph (, )][DBLP]
    
    
25. 
    Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. [Citation Graph (, )][DBLP]
    
    
26. 
    DC-SIMD : Dynamic communication for SIMD processors. [Citation Graph (, )][DBLP]
    
    
27. 
    Performance evaluation of concurrently executing parallel applications on multi-processor systems. [Citation Graph (, )][DBLP]
    
    
28. 
    Enabling MPSoC Design Space Exploration on FPGAs. [Citation Graph (, )][DBLP]