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Renaud Pacalet: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet
    A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:86-95 [Conf]
  2. Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
    Differential Power Analysis Model and Some Results. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:127-142 [Conf]
  3. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
    The "Backend Duplication" Method. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:383-397 [Conf]
  4. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
    CMOS Structures Suitable for Secured Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1414-1415 [Conf]
  5. Muhammad Waseem, Ludovic Apvrille, Rabea Ameur-Boulifa, Sophie Coudert, Renaud Pacalet
    Abstract Application Modeling for System Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:331-337 [Conf]
  6. Stéphane Mancini, Renaud Pacalet
    LUX: An Heterogeneous Function Composition Parallel Computer for Graphics. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:940-949 [Conf]
  7. Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
    A fast pipelined multi-mode DES architecture operating in IP representation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:479-489 [Journal]

  8. Optimum LDPC decoder: a memory architecture problem. [Citation Graph (, )][DBLP]

  9. SecBus: Operating System controlled hierarchical page-based memory bus protection. [Citation Graph (, )][DBLP]

  10. Flexible Baseband Architectures for Future Wireless Systems. [Citation Graph (, )][DBLP]

  11. Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques. [Citation Graph (, )][DBLP]

  12. Silicon-level Solutions to Counteract Passive and Active Attacks. [Citation Graph (, )][DBLP]

  13. High-Level System Modeling for Rapid HW/SW Architecture Exploration. [Citation Graph (, )][DBLP]

  14. Evaluation of ASIPs Design with LISATek. [Citation Graph (, )][DBLP]

  15. Fast Simulation Techniques for Design Space Exploration. [Citation Graph (, )][DBLP]

  16. Application Specific Processors for Multimedia Applications. [Citation Graph (, )][DBLP]

  17. Formal System-level Design Space Exploration. [Citation Graph (, )][DBLP]

  18. Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. [Citation Graph (, )][DBLP]

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