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Wilhelmus A. M. Van Noije: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marco Antonio Dal Poz, J. Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo
    A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:35-0 [Conf]
  2. João Navarro Jr., Wilhelmus A. M. Van Noije
    CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:89-94 [Conf]
  3. João Navarro Jr., Wilhelmus A. M. Van Noije
    Design of an 8: 1 MUX at 1.7Gbit/s in 0.8?I`m CMOS Technology. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:103-107 [Conf]
  4. João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije
    A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:14-0 [Conf]
  5. Luis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. V. Noije
    Ultra low-voltage ultra low-power CMOS threshold voltage reference. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:80-82 [Conf]
  6. Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije
    A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:144-148 [Conf]
  7. Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
    A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:94-99 [Conf]
  8. Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije
    A Methodology for CMOS Low Noise Ampli.er Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:14-19 [Conf]
  9. Augusto Ken Morita, Marcio Toma, Wilhelmus A. M. Van Noije
    Implementação de Um Sistema de Decriptografia para Controle Bancário em Hardware tipo FPGA. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:63-81 [Journal]
  10. Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
    A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1895-1898 [Conf]
  11. A. J. Aragao, João Navarro Jr., Wilhelmus A. M. Van Noije
    Mismatch effect analyses in CMOS tapered buffers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  12. João Navarro Jr., Wilhelmus A. M. Van Noije
    Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:301-308 [Journal]

  13. A 4.1 GHz prescaler using double data throughput E-TSPC structures. [Citation Graph (, )][DBLP]


  14. A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. [Citation Graph (, )][DBLP]


  15. An improved and automated design tool for the optimization of CMOS OTAs using geometric programming. [Citation Graph (, )][DBLP]


  16. A 2.7ua sub1-v voltage reference. [Citation Graph (, )][DBLP]


  17. A low-voltage bandgap reference source based on the current-mode technique. [Citation Graph (, )][DBLP]


  18. Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology. [Citation Graph (, )][DBLP]


  19. A merged RF CMOS LNA-Mixer design using geometric programming. [Citation Graph (, )][DBLP]


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