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Rama Sangireddy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rama Sangireddy
    Register Organization for Enhanced On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:180-190 [Conf]
  2. Rama Sangireddy, Arun K. Somani
    Application-Specific Computing with Adaptive Register File Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:183-0 [Conf]
  3. Rama Sangireddy, Huesung Kim, Arun K. Somani
    Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:124-136 [Conf]
  4. Rama Sangireddy, Huesung Kim, Arun K. Somani
    Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:23-33 [Conf]
  5. Rama Sangireddy, Arun K. Somani
    Exploiting Quiescent States in Register Lifetime. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:368-374 [Conf]
  6. Rama Sangireddy
    Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:227-232 [Conf]
  7. Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam
    Performance Optimization with Scalable Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:381-386 [Conf]
  8. Rama Sangireddy
    Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:6, pp:672-685 [Journal]
  9. Rama Sangireddy, Huesung Kim, Arun K. Somani
    Low-Power High-Performance Reconfigurable Computing Cache Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:10, pp:1274-1290 [Journal]
  10. Rama Sangireddy, Natsuhiko Futamura, Srinivas Aluru, Arun K. Somani
    Scalable, memory efficient, high-speed IP lookup algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:4, pp:802-812 [Journal]
  11. Rama Sangireddy
    Register port complexity reduction in wide-issue processors with selective instruction execution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:1, pp:51-62 [Journal]
  12. Jatan Shah, Rama Sangireddy
    Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4012-4015 [Conf]
  13. Rama Sangireddy
    Fast and low-power processor front-end with reduced rename logic circuit complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  14. Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. [Citation Graph (, )][DBLP]


  15. An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. [Citation Graph (, )][DBLP]


  16. High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. [Citation Graph (, )][DBLP]


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