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Rodolfo Azevedo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ricardo Santos, Rodolfo Azevedo, Guido Araujo
    2D-VLIW: An Architecture Based on the Geometry of Computation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:87-94 [Conf]
  2. Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:141-148 [Conf]
  3. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-profile based code compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:244-249 [Conf]
  4. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:734-735 [Conf]
  5. Edson Borin, Felipe Klein, Nahri Moreano, Rodolfo Azevedo, Guido Araujo
    Fast instruction set custornization. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:53-58 [Conf]
  6. Ricardo Santos, Rodolfo Azevedo, Guido Araujo
    Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  7. Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos
    On the Limitations of Power Macromodeling Techniques. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:395-400 [Conf]
  8. Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:351-356 [Conf]
  9. Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo
    Optimizations for Compiled Simulation Using Instruction Type Information. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:74-81 [Conf]
  10. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Exploring Memory Hierarchy with ArchC. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:2-9 [Conf]
  11. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-Profile Instruction Based Compression. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:23-29 [Conf]
  12. Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo
    ArchC: A SystemC-Based Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:66-73 [Conf]
  13. Richard E. Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Wanderley Netto
    Design of a decompressor engine on a SPARC processor. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:110-114 [Conf]
  14. Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araujo, Edna Barros
    The ArchC Architecture Description Language and Tools. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:5, pp:453-484 [Journal]
  15. Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:123-129 [Conf]
  16. Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain
    Expression-tree-based algorithms for code compression on embedded RISC architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:530-533 [Journal]

  17. A multi-model power estimation engine for accuracy optimization. [Citation Graph (, )][DBLP]


  18. STM versus lock-based systems: an energy consumption perspective. [Citation Graph (, )][DBLP]


  19. A Software Transactional Memory System for an Asymmetric Processor Architecture. [Citation Graph (, )][DBLP]


  20. On the energy-efficiency of software transactional memory. [Citation Graph (, )][DBLP]


  21. Processor Centric Specification and Modelling of MPSoCs. [Citation Graph (, )][DBLP]


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