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Guido Araujo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ricardo Santos, Rodolfo Azevedo, Guido Araujo
    2D-VLIW: An Architecture Based on the Geometry of Computation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:87-94 [Conf]
  2. Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:141-148 [Conf]
  3. Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
    Optimal Live Range Merge for Address Register Allocation in Embedded Programs. [Citation Graph (0, 0)][DBLP]
    CC, 2001, pp:274-288 [Conf]
  4. Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo
    Software-Based Transparent and Comprehensive Control-Flow Error Detection. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:333-345 [Conf]
  5. Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
    Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:591-596 [Conf]
  6. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-profile based code compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:244-249 [Conf]
  7. Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang
    Challenges in code generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:48-64 [Conf]
  8. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:734-735 [Conf]
  9. Edson Borin, Felipe Klein, Nahri Moreano, Rodolfo Azevedo, Guido Araujo
    Fast instruction set custornization. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:53-58 [Conf]
  10. Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab
    A custom instruction approach for hardware and software implementations of finite field arithmetic over F263 using Gaussian normal bases. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:5-12 [Conf]
  11. Ricardo Santos, Rodolfo Azevedo, Guido Araujo
    Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  12. Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano
    Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:38-43 [Conf]
  13. Guido Araujo, Ashok Sudarsanam, Sharad Malik
    Instruction Set Design and Optimizations for Address Computation in DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:102-107 [Conf]
  14. Paulo Centoducatte, Ricardo Pannain, Guido Araujo
    Compressed Code Execution on DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:56-63 [Conf]
  15. Guido Araujo, Sharad Malik
    Optimal code generation for embedded memory non-homogeneous register architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:36-41 [Conf]
  16. Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos
    On the Limitations of Power Macromodeling Techniques. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:395-400 [Conf]
  17. Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:351-356 [Conf]
  18. Marcelo Silva Cintra, Guido Araujo
    Array Reference Allocation Using SSA-Form and Live Range Growth. [Citation Graph (0, 0)][DBLP]
    LCTES, 2000, pp:48-62 [Conf]
  19. Guido Araujo, Paulo Centoducatte, Mario Cartes, Ricardo Pannain
    Code Compression Based on Operand Factorization. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:194-201 [Conf]
  20. Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo
    Optimizations for Compiled Simulation Using Instruction Type Information. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:74-81 [Conf]
  21. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Exploring Memory Hierarchy with ArchC. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:2-9 [Conf]
  22. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-Profile Instruction Based Compression. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:23-29 [Conf]
  23. Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo
    ArchC: A SystemC-Based Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:66-73 [Conf]
  24. Richard E. Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Wanderley Netto
    Design of a decompressor engine on a SPARC processor. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:110-114 [Conf]
  25. Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta
    An automatic testbench generation tool for a SystemC functional verification methodology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:66-70 [Conf]
  26. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
    Improving Offset Assignment through Simultaneous Variable Coalescing. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:285-297 [Conf]
  27. Cid C. de Souza, André M. Lima, Nahri Moreano, Guido Araujo
    The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation. [Citation Graph (0, 0)][DBLP]
    WEA, 2004, pp:545-558 [Conf]
  28. Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araujo, Edna Barros
    The ArchC Architecture Description Language and Tools. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:5, pp:453-484 [Journal]
  29. Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano
    The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2005, v:10, n:, pp:- [Journal]
  30. Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo
    Efficient datapath merging for partially reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:969-980 [Journal]
  31. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
    A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]
  32. Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo
    The design of dynamically reconfigurable datapath coprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:361-384 [Journal]
  33. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
    Offset assignment using simultaneous variable coalescing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:4, pp:864-883 [Journal]
  34. Guido Araujo, Sharad Malik
    Code generation for fixed-point DSPs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:136-161 [Journal]
  35. Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra
    Global array reference allocation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:336-357 [Journal]
  36. Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:123-129 [Conf]
  37. Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain
    Expression-tree-based algorithms for code compression on embedded RISC architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:530-533 [Journal]
  38. Guilherme Ottoni, Guido Araujo
    Address register allocation for arrays in loops of embedded programs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1009-1018 [Journal]
  39. Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab
    A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:59-76 [Journal]

  40. A computational reflection mechanism to support platform debugging in SystemC. [Citation Graph (, )][DBLP]


  41. Reducing False Aborts in STM Systems. [Citation Graph (, )][DBLP]


  42. Clustering-Based Microcode Compression. [Citation Graph (, )][DBLP]


  43. A multi-model power estimation engine for accuracy optimization. [Citation Graph (, )][DBLP]


  44. On the energy-efficiency of software transactional memory. [Citation Graph (, )][DBLP]


  45. Processor Centric Specification and Modelling of MPSoCs. [Citation Graph (, )][DBLP]


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