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Sergej Sawitzki:
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- Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
Formal Verification for Microprocessors with Extendable Instruction Set. [Citation Graph (0, 0)][DBLP] ASAP, 2000, pp:47-55 [Conf]
- John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf
Power-efficient layered turbo decoder processor. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:246-251 [Conf]
- Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube
Formal Verification of a Reconfigurable Microprocessor. [Citation Graph (0, 0)][DBLP] FPL, 2000, pp:781-784 [Conf]
- Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:411-415 [Conf]
- Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek
Prototyping Framework for Reconfigurable Processors. [Citation Graph (0, 0)][DBLP] FPL, 2001, pp:6-16 [Conf]
- Sergej Sawitzki, Rainer G. Spallek
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] FPL, 2003, pp:1119-1122 [Conf]
- Sergej Sawitzki, Rainer G. Spallek
A Concept for an Evaluation Framework for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP] FPL, 1999, pp:475-480 [Conf]
- Sergej Sawitzki
Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme. [Citation Graph (0, 0)][DBLP] GI Jahrestagung, 1999, pp:239-246 [Conf]
- Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek
Improving Code Efficiency for Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP] IPDPS, 2002, pp:- [Conf]
- Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. [Citation Graph (0, 0)][DBLP] IPPS/SPDP Workshops, 1999, pp:706-708 [Conf]
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