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Sven Simon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christian V. Schimpfle, Sven Simon, Josef A. Nossek
    Low Power CORDIC Implementation Using Redundant Number Representation. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:154-161 [Conf]
  2. Andreas Wortmann, Sven Simon, Matthias Müller
    A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:46-51 [Conf]
  3. Matthias Müller, Sven Simon
    Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:457- [Conf]
  4. Sven Simon, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek
    A New Retiming Algorithm for Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:35-38 [Conf]
  5. Sven Simon, Johann Hofner, Josef A. Nossek
    Retiming of Circuits Containing Multiplexers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1736-1739 [Conf]
  6. Marek Wróblewski, Matthias Müller, Andreas Wortmann, Sven Simon, Wilhelm Pieper, Josef A. Nossek
    A power efficient register file architecture using master latch sharing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:393-396 [Conf]
  7. Sven Simon, Marek Wróblewski
    Low power datapath design using transformation similar to temporal localization of SFGs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:59-61 [Conf]
  8. Christian V. Schimpfle, Sven Simon, Josef A. Nossek
    Device level based cell modeling for fast power estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:90-93 [Conf]
  9. Sven Simon, Matthias Müller, Holger Gryska, Andreas Wortmann, Steffen Buch
    An instruction set for the efficient implementation of the CORDIC algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:357-360 [Conf]
  10. Matthias Müller, Andreas Wortmann, Sven Simon, Michael Kugel, Tim Schoenauer
    The impact of clock gating schemes on the power dissipation of synthesizable register files. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:609-612 [Conf]
  11. Matthias Müller, Andreas Wortmann, Sven Simon, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek
    Low power register file architecture for application specific DSPs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:89-92 [Conf]
  12. Matthias Müller, Andreas Wortmann, Dominik Mader, Sven Simon
    Register Isolation for Synthesizable Register Files. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:228-237 [Conf]
  13. Sven Simon, Ralf Bucher, Josef A. Nossek
    Retiming of synchronous circuits with variable topology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:130-134 [Conf]
  14. Matthias Müller, Sven Simon, Holger Gryska, Andreas Wortmann, Steffen Buch
    Low power synthesizable register files for processor and IP cores. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:131-155 [Journal]

  15. Using Arithmetic Coding for Reduction of Resulting Simulation Data Size on Massively Parallel GPGPUs. [Citation Graph (, )][DBLP]


  16. Accelerating Simulations of Light Scattering Based on Finite-Difference Time-Domain Method with General Purpose GPUs. [Citation Graph (, )][DBLP]


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