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Publications of Author

1. Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
   High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
   ASAP, 2000, pp:113-0 [Conf]
   
2. Shail Aditya, Michael S. Schlansker
   ShiftQ: a bufferred interconnect for custom loop accelerators. [Citation Graph (0, 0)][DBLP]
   CASES, 2001, pp:158-167 [Conf]
   
3. Mukund Sivaraman, Shail Aditya
   Cycle-time aware architecture synthesis of custom hardware accelerators. [Citation Graph (0, 0)][DBLP]
   CASES, 2002, pp:35-42 [Conf]
   
4. Shail Aditya, Arvind, Joseph E. Stoy
   Semantics of Barriers in a Non-Strict, Implicitly-Parallel Language. [Citation Graph (0, 0)][DBLP]
   FPCA, 1995, pp:204-215 [Conf]
   
5. Shail Aditya, Alejandro Caro
   Compiler-directed Type Reconstruction for Polymorphic Languages. [Citation Graph (0, 0)][DBLP]
   FPCA, 1993, pp:74-82 [Conf]
   
6. Shail Aditya, Rishiyur S. Nikhil
   Incremental Polymorphism. [Citation Graph (0, 0)][DBLP]
   FPCA, 1991, pp:379-405 [Conf]
   
7. Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
   Automatic Architectural Synthesis of VLIW and EPIC Processors. [Citation Graph (0, 0)][DBLP]
   ISSS, 1999, pp:107-113 [Conf]
   
8. Arvind, Alejandro Caro, Jan-Willem Maessen, Shail Aditya
   A Multithreaded Substrate and Compilation Model for the Implicity Parallel Language pH. [Citation Graph (0, 0)][DBLP]
   LCPC, 1996, pp:519-533 [Conf]
   
9. Shail Aditya, Christine H. Flood, James E. Hicks
   Garbage Collection for Strongly-Typed Languages Using Run-Time Type Reconstruction. [Citation Graph (0, 0)][DBLP]
   LISP and Functional Programming, 1994, pp:12-23 [Conf]
   
10. Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar
    Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:12- [Conf]
    
11. Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
    PICO: Automatically Designing Custom Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:9, pp:39-47 [Journal]
    
12. Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau
    Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:752-773 [Journal]