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B. Ramakrishna Rau: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
    High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:113-0 [Conf]
  2. Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:238-247 [Conf]
  3. B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt
    Architectural Support for the Efficient Generation of Code for Horizontal Architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:96-99 [Conf]
  4. Santosh G. Abraham, B. Ramakrishna Rau
    Efficient design space exploration in PICO. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:71-79 [Conf]
  5. B. Ramakrishna Rau
    The era of embedded computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:119- [Conf]
  6. B. R. Rau
    Cydra 5 Directed Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1988, pp:106-113 [Conf]
  7. B. Ramakrishna Rau, Michael S. Schlansker
    Embedded Computing: New Directions in Architecture and Automation. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:225-244 [Conf]
  8. B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen
    The Cydram 5 Stride-Insensitive Memory System. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:242-246 [Conf]
  9. Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
    A Constructive Solution to the Juggling Problem in Processor Array Synthesis. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:815-822 [Conf]
  10. B. Ramakrishna Rau
    Pseudo-Randomly Interleaved Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:74-83 [Conf]
  11. B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard
    Efficient code generation for horizontal architectures: Compiler techniques and architectural support. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:131-139 [Conf]
  12. B. Ramakrishna Rau, George E. Rossman
    The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. [Citation Graph (0, 0)][DBLP]
    ISCA, 1977, pp:80-89 [Conf]
  13. Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
    Automatic Architectural Synthesis of VLIW and EPIC Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:107-113 [Conf]
  14. B. Ramakrishna Rau
    Data Flow and Dependence Analysis for Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 1991, pp:236-250 [Conf]
  15. Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta
    Predictability of load/store instruction latencies. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:139-152 [Conf]
  16. B. Ramakrishna Rau
    Dynamically scheduled VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:80-92 [Conf]
  17. B. Ramakrishna Rau
    Iterative modulo scheduling: an algorithm for software pipelining loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:63-74 [Conf]
  18. Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
    Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:58-67 [Conf]
  19. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
    Optimization of Machine Descriptions for Efficient Use. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:349-358 [Conf]
  20. Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
    Region-based compilation: an introduction and motivation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:158-168 [Conf]
  21. B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
    Code generation schema for modulo scheduled loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:158-169 [Conf]
  22. B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
    Register Allocation for Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 1992, pp:283-299 [Conf]
  23. Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau
    Reverse If-Conversion. [Citation Graph (0, 0)][DBLP]
    PLDI, 1993, pp:290-299 [Conf]
  24. Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
    PICO: Automatically Designing Custom Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:9, pp:39-47 [Journal]
  25. B. Ramakrishna Rau, Michael S. Schlansker
    Embedded Computer Architecture and Automation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:75-83 [Journal]
  26. B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle
    The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:1, pp:12-35 [Journal]
  27. Michael S. Schlansker, B. Ramakrishna Rau
    EPIC: Explicititly Parallel Instruction Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:2, pp:37-45 [Journal]
  28. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
    Optimization of Machine Descriptions for Efficient Use. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:417-447 [Journal]
  29. B. Ramakrishna Rau
    Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:678-681 [Journal]
  30. B. Ramakrishna Rau
    Program Behavior and the Performance of Interleaved Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:3, pp:191-199 [Journal]
  31. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:376-408 [Journal]
  32. Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau
    Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:752-773 [Journal]
  33. Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
    Constructing and exploiting linear schedules with prescribed parallelism. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:159-172 [Journal]

  34. Systematically derived instruction sets for high-level language support. [Citation Graph (, )][DBLP]


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