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Vinod Kathail: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
    High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:113-0 [Conf]
  2. Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
    Automatic Architectural Synthesis of VLIW and EPIC Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:107-113 [Conf]
  3. Michael S. Schlansker, Vinod Kathail
    Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 1993, pp:406-429 [Conf]
  4. Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
    Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:308-321 [Conf]
  5. Michael S. Schlansker, Vinod Kathail
    Critical path reduction for scalar programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:57-69 [Conf]
  6. Michael S. Schlansker, Vinod Kathail, Sadun Anik
    Height reduction of control recurrences for ILP processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:40-51 [Conf]
  7. Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari
    Fine Grained Register Allocation for EPIC Processors With Predication. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:2760-2766 [Conf]
  8. Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar
    Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:12- [Conf]
  9. Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
    PICO: Automatically Designing Custom Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:9, pp:39-47 [Journal]
  10. Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
    Meld Scheduling: A Technique for Relaxing Scheduling Constraints. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:349-381 [Journal]

  11. Programming high performance signal processing systems in high level languages. [Citation Graph (, )][DBLP]

  12. Architecture Exploration for Low Power Design. [Citation Graph (, )][DBLP]

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