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Ahmed M. Shams: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ahmed M. Shams, Magdy A. Bayoumi
    A 108 Gbps, 1.5 GHz 1D-DCT Architecture. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:163-172 [Conf]
  2. Ahmed M. Shams, Mohamed A. Elgamel, Magdy A. Bayoumi
    Hybrid Mesh-Based/Block-Based Motion Compensation Architecture. [Citation Graph (0, 0)][DBLP]
    Workshop on Digital and Computational Video, 2001, pp:194-201 [Conf]
  3. Ahmed M. Shams, Magdy A. Bayoumi
    A New Full Adder Cell for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:45-0 [Conf]
  4. Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi
    Enhanced low power motion estimation VLSI architectures for video compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:474-477 [Conf]
  5. Ahmed M. Shams, Magdy A. Bayoumi
    Performance evaluation of 1-bit CMOS adder cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:27-30 [Conf]
  6. Ahmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi
    A Low Power High Performance Distributed DCT Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:26-34 [Conf]
  7. Mohamed A. Elgamel, Magdy A. Bayoumi, Ahmed M. Shams, Bertrand Zavidovique
    Low Power Full Search Block Matching Motion Estimation Vlsi Architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:6, pp:1271-1288 [Journal]
  8. Ahmed M. Shams, T. K. Darwish, Magdy A. Bayoumi
    Performance analysis of low-power 1-bit CMOS full adder cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:20-29 [Journal]

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