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Jari Nurmi :
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Piia Simonen , Ilkka Saastamoinen , Jari Nurmi Variable-Length Instruction Compression for Area Minimization. [Citation Graph (0, 0)][DBLP ] ASAP, 2003, pp:155-160 [Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi A parallel configuration model for reducing the run-time reconfiguration overhead. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:965-969 [Conf ] Heikki Kariniemi , Jari Nurmi Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip. [Citation Graph (0, 0)][DBLP ] DDECS, 2006, pp:186-191 [Conf ] Ilkka Saastamoinen , David A. Sigüenza-Tortosa , Jari Nurmi Interconnect IP Node for Future System-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:116-122 [Conf ] Piia Simonen , Ilkka Saastamoinen , Mika Kuulusa , Jari Nurmi Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:477-479 [Conf ] Tapani Ahonen , Jari Nurmi Integration of a NoC-Based Multimedia Processing Platform. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:606-611 [Conf ] Heikki Kariniemi , Jari Nurmi Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:203-210 [Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:648-653 [Conf ] Tapio Ristimäki , Jari Nurmi Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP ] FPL, 2004, pp:1130-1132 [Conf ] Jouni Isoaho , Jari Nurmi An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:265-268 [Conf ] Heikki Kariniemi , Jari Nurmi Improved multicast switch architecture for optical cable television and video surveillance networks. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2004, pp:221-224 [Conf ] Christian Panis , Raimund Leitner , Herbert Grünbacher , Jari Nurmi xLIW - a scaleable long instruction word. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:69-72 [Conf ] Ilkka Saastamoinen , M. Alho , Jari Nurmi Buffer implementation for Proteo network-on-chip. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2003, pp:113-116 [Conf ] Juhani Vehvilainen , Jari Nurmi A Processor Core for 32 kbit/s G.726 ADPCM Codecs. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:1932-1935 [Conf ] Maini Williams , Jari Nurmi Multipurpose Chip for Physiological Measurements. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:255-258 [Conf ] L. Harju , J. Nurmi A baseband receiver architecture for UMTS-WLAN interworking applications. [Citation Graph (0, 0)][DBLP ] ISCC, 2004, pp:678-685 [Conf ] Tapani Ahonen , Tero Nurmi , Jari Nurmi , Jouni Isoaho Block-wise Extraction of Rent's Exponents for an Extensible Processor. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2003, pp:193-202 [Conf ] Christian Panis , Ulrich Hirnschrott , Andreas Krall , Gunther Laure , Wolfgang Lazian , Jari Nurmi FSEL - Selective Predicated Execution for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2004, pp:317-320 [Conf ] Christian Panis , Raimund Leitner , Jari Nurmi Scaleable Shadow Stack for a Configurable DSP Concept. [Citation Graph (0, 0)][DBLP ] IWSOC, 2003, pp:222-227 [Conf ] Jari Nurmi , Jan Madsen , Erwin Ofner , Jouni Isoaho , Hannu Tenhunen The SoC-Mobinet Model in System-on-Chip Education. [Citation Graph (0, 0)][DBLP ] MSE, 2005, pp:71-72 [Conf ] David A. Sigüenza-Tortosa , Jari Nurmi Packet scheduling in proteo network-on-chip. [Citation Graph (0, 0)][DBLP ] Parallel and Distributed Computing and Networks, 2004, pp:116-121 [Conf ] Claudio Brunelli , Fabio Garzia , Jari Nurmi A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2006, pp:1-7 [Conf ] David A. Sigüenza-Tortosa , Jari Nurmi System Monitoring and Reconfiguration in Proteo NoC. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2005, pp:99-104 [Conf ] Christian Panis , Ulrich Hirnschrott , Gunther Laure , Wolfgang Lazian , Jari Nurmi DSPxPlore: design space exploration methodology for an embedded DSP core. [Citation Graph (0, 0)][DBLP ] SAC, 2004, pp:876-883 [Conf ] Tapani Ahonen , David A. Sigüenza-Tortosa , Hong Bin , Jari Nurmi Topology optimization for application-specific networks-on-chip. [Citation Graph (0, 0)][DBLP ] SLIP, 2004, pp:53-60 [Conf ] Christian Panis , Gunther Laure , Wolfgang Lazian , Herbert Grünbacher , Jari Nurmi A Branch File for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:7-12 [Conf ] Tapio Ristimäki , Jari Nurmi Reprogrammable Algorithm Accelerator IP Block. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:228-232 [Conf ] Heikki Kariniemi , Jari Nurmi Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal ] Mika Kuulusa , Jari Nurmi , Janne Takala , Pasi Ojala , Henrik Herranen A Flexible DSP Core for Embedded Systems. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1997, v:14, n:4, pp:60-68 [Journal ] David A. Sigüenza-Tortosa , Tapani Ahonen , Jari Nurmi Issues in the development of a practical NoC: the Proteo concept. [Citation Graph (0, 0)][DBLP ] Integration, 2004, v:38, n:1, pp:95-105 [Journal ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:147-152 [Conf ] Xin Wang , Tapani Ahonen , Jari Nurmi Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. [Citation Graph (0, 0)][DBLP ] FPL, 2006, pp:1-6 [Conf ] Heikki Kariniemi , Jari Nurmi On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. [Citation Graph (0, 0)][DBLP ] FPL, 2006, pp:1-6 [Conf ] Yang Qu , Kari Tiensyrjä , Juha-Pekka Soininen , Jari Nurmi System-Level Design for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:2738-2741 [Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:161-164 [Conf ] Fabio Garzia , Claudio Brunelli , Andrea Ferro , Jari Nurmi Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2007, pp:166-170 [Conf ] Sanna Määttä , Jari Nurmi Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2007, pp:84-89 [Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2007, v:53, n:11, pp:861-876 [Journal ] Xin Wang , Tapani Ahonen , Jari Nurmi Applying CDMA Technique to Network-on-Chip. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1091-1100 [Journal ] Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking. [Citation Graph (, )][DBLP ] A VHDL-based bus model for multi-PCB system design. [Citation Graph (, )][DBLP ] Reconfigurable hardware: The holy grail of matching performance with programming productivity. [Citation Graph (, )][DBLP ] A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. [Citation Graph (, )][DBLP ] CREMA: A coarse-grain reconfigurable array with mapping adaptiveness. [Citation Graph (, )][DBLP ] Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. [Citation Graph (, )][DBLP ] Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. [Citation Graph (, )][DBLP ] A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP ] Mobile WiMAX Handover Performance Evaluation. [Citation Graph (, )][DBLP ] Validation of executable application models mapped onto network-on-chip platforms. [Citation Graph (, )][DBLP ] A Wireless MIMO STC OFDM System Implementation. [Citation Graph (, )][DBLP ] Realization of Free Viewpoint TV Based on Improved MVC. [Citation Graph (, )][DBLP ] SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel. [Citation Graph (, )][DBLP ] Optimal dual frequency combination for Galileo mass market receiver baseband. [Citation Graph (, )][DBLP ] Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios. [Citation Graph (, )][DBLP ] Conference Reports. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.308secs