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Jari Nurmi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Piia Simonen, Ilkka Saastamoinen, Jari Nurmi
    Variable-Length Instruction Compression for Area Minimization. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:155-160 [Conf]
  2. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    A parallel configuration model for reducing the run-time reconfiguration overhead. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:965-969 [Conf]
  3. Heikki Kariniemi, Jari Nurmi
    Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:186-191 [Conf]
  4. Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi
    Interconnect IP Node for Future System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:116-122 [Conf]
  5. Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, Jari Nurmi
    Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:477-479 [Conf]
  6. Tapani Ahonen, Jari Nurmi
    Integration of a NoC-Based Multimedia Processing Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:606-611 [Conf]
  7. Heikki Kariniemi, Jari Nurmi
    Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:203-210 [Conf]
  8. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:648-653 [Conf]
  9. Tapio Ristimäki, Jari Nurmi
    Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1130-1132 [Conf]
  10. Jouni Isoaho, Jari Nurmi
    An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:265-268 [Conf]
  11. Heikki Kariniemi, Jari Nurmi
    Improved multicast switch architecture for optical cable television and video surveillance networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:221-224 [Conf]
  12. Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi
    xLIW - a scaleable long instruction word. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:69-72 [Conf]
  13. Ilkka Saastamoinen, M. Alho, Jari Nurmi
    Buffer implementation for Proteo network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:113-116 [Conf]
  14. Juhani Vehvilainen, Jari Nurmi
    A Processor Core for 32 kbit/s G.726 ADPCM Codecs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1932-1935 [Conf]
  15. Maini Williams, Jari Nurmi
    Multipurpose Chip for Physiological Measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:255-258 [Conf]
  16. L. Harju, J. Nurmi
    A baseband receiver architecture for UMTS-WLAN interworking applications. [Citation Graph (0, 0)][DBLP]
    ISCC, 2004, pp:678-685 [Conf]
  17. Tapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho
    Block-wise Extraction of Rent's Exponents for an Extensible Processor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:193-202 [Conf]
  18. Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi
    FSEL - Selective Predicated Execution for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:317-320 [Conf]
  19. Christian Panis, Raimund Leitner, Jari Nurmi
    Scaleable Shadow Stack for a Configurable DSP Concept. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:222-227 [Conf]
  20. Jari Nurmi, Jan Madsen, Erwin Ofner, Jouni Isoaho, Hannu Tenhunen
    The SoC-Mobinet Model in System-on-Chip Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:71-72 [Conf]
  21. David A. Sigüenza-Tortosa, Jari Nurmi
    Packet scheduling in proteo network-on-chip. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2004, pp:116-121 [Conf]
  22. Claudio Brunelli, Fabio Garzia, Jari Nurmi
    A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:1-7 [Conf]
  23. David A. Sigüenza-Tortosa, Jari Nurmi
    System Monitoring and Reconfiguration in Proteo NoC. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:99-104 [Conf]
  24. Christian Panis, Ulrich Hirnschrott, Gunther Laure, Wolfgang Lazian, Jari Nurmi
    DSPxPlore: design space exploration methodology for an embedded DSP core. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:876-883 [Conf]
  25. Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi
    Topology optimization for application-specific networks-on-chip. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:53-60 [Conf]
  26. Christian Panis, Gunther Laure, Wolfgang Lazian, Herbert Grünbacher, Jari Nurmi
    A Branch File for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:7-12 [Conf]
  27. Tapio Ristimäki, Jari Nurmi
    Reprogrammable Algorithm Accelerator IP Block. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:228-232 [Conf]
  28. Heikki Kariniemi, Jari Nurmi
    Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  29. Mika Kuulusa, Jari Nurmi, Janne Takala, Pasi Ojala, Henrik Herranen
    A Flexible DSP Core for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:60-68 [Journal]
  30. David A. Sigüenza-Tortosa, Tapani Ahonen, Jari Nurmi
    Issues in the development of a practical NoC: the Proteo concept. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:95-105 [Journal]
  31. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:147-152 [Conf]
  32. Xin Wang, Tapani Ahonen, Jari Nurmi
    Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  33. Heikki Kariniemi, Jari Nurmi
    On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  34. Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi
    System-Level Design for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2738-2741 [Conf]
  35. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:161-164 [Conf]
  36. Fabio Garzia, Claudio Brunelli, Andrea Ferro, Jari Nurmi
    Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:166-170 [Conf]
  37. Sanna Määttä, Jari Nurmi
    Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:84-89 [Conf]
  38. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:11, pp:861-876 [Journal]
  39. Xin Wang, Tapani Ahonen, Jari Nurmi
    Applying CDMA Technique to Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1091-1100 [Journal]

  40. Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking. [Citation Graph (, )][DBLP]

  41. A VHDL-based bus model for multi-PCB system design. [Citation Graph (, )][DBLP]

  42. Reconfigurable hardware: The holy grail of matching performance with programming productivity. [Citation Graph (, )][DBLP]

  43. A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. [Citation Graph (, )][DBLP]

  44. CREMA: A coarse-grain reconfigurable array with mapping adaptiveness. [Citation Graph (, )][DBLP]

  45. Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. [Citation Graph (, )][DBLP]

  46. Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. [Citation Graph (, )][DBLP]

  47. A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP]

  48. Mobile WiMAX Handover Performance Evaluation. [Citation Graph (, )][DBLP]

  49. Validation of executable application models mapped onto network-on-chip platforms. [Citation Graph (, )][DBLP]

  50. A Wireless MIMO STC OFDM System Implementation. [Citation Graph (, )][DBLP]

  51. Realization of Free Viewpoint TV Based on Improved MVC. [Citation Graph (, )][DBLP]

  52. SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel. [Citation Graph (, )][DBLP]

  53. Optimal dual frequency combination for Galileo mass market receiver baseband. [Citation Graph (, )][DBLP]

  54. Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios. [Citation Graph (, )][DBLP]

  55. Conference Reports. [Citation Graph (, )][DBLP]

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