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Kazuo Nakajima: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima
    A Component Architecture for FPGA-Based, DSP System Design. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:41-0 [Conf]
  2. Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima
    Via Minimization for Gridless Layouts. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:159-165 [Conf]
  3. Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima
    A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:665-674 [Conf]
  4. Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
    Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:428-431 [Conf]
  5. Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato
    A New Model for Over-The-Cell Channel Routing with Three Layers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:432-435 [Conf]
  6. Jagannathan Narasimhan, Kazuo Nakajima
    A Reconfiguration-Based Yield Enhancement System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:224-228 [Conf]
  7. Young-Jun Cha, Chong S. Rim, Kazuo Nakajima
    A simple and effective greedy multilayer router for MCMs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:67-72 [Conf]
  8. Jagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim
    A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:195-221 [Journal]
  9. Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa
    Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1992, v:13, n:1, pp:161-174 [Journal]
  10. Kazuo Nakajima, S. Louis Hakimi
    Complexity Results for Scheduling Tasks with Discrete Starting Times. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1982, v:3, n:4, pp:344-361 [Journal]
  11. Ruey-Der Lou, Majid Sarrafzadeh, Chong S. Rim, Kazuo Nakajima, Sumio Masuda
    General Circular Permutation Layout. [Citation Graph (0, 0)][DBLP]
    Mathematical Systems Theory, 1992, v:25, n:4, pp:269-292 [Journal]
  12. Hirokazu Kotani, Akira Kawamura, Asako Takahashi, Masako Nakatsuji, Nobutsugu Hiraoka, Kazuo Nakajima, Mituru Takanami
    Site-specific dissection of E. coli chromosome by lambda terminase. [Citation Graph (0, 0)][DBLP]
    Nucleic Acids Research, 1992, v:20, n:13, pp:3357-3360 [Journal]
  13. Sumio Masuda, Kazuo Nakajima
    An Optimal Algorithm for Finding a Maximum Independent Set of a Circular-Arc Graph. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1988, v:17, n:1, pp:41-52 [Journal]
  14. Hyeong-Ah Choi, Kazuo Nakajima, Chong S. Rim
    Graph Bipartization and via Minimization. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 1989, v:2, n:1, pp:38-47 [Journal]
  15. S. Louis Hakimi, Kazuo Nakajima
    On Adaptive System Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:3, pp:234-240 [Journal]
  16. Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Thio Fujisawa
    Crossing Minimization in Linear Embeddings of Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:1, pp:124-127 [Journal]
  17. Jagannathan Narasimhan, Kazuo Nakajima
    An Algorithm for Determining the Fault Diagnosability of a System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:11, pp:1004-1008 [Journal]
  18. Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima
    The Via Minimization Problem is NP-Complete. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:11, pp:1604-1608 [Journal]
  19. Young-Jun Cha, Chong S. Rim, Kazuo Nakajima
    SEGRA: a very fast general area router for multichip modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:659-665 [Journal]
  20. J. Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura
    Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:976-986 [Journal]
  21. Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima
    Exact algorithms for multilayer topological via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1165-1173 [Journal]
  22. Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
    Min-cut placement with global objective functions for large scale sea-of-gates arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:434-446 [Journal]
  23. Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato
    A new approach to over-the-cell channel routing with three layers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:187-200 [Journal]

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