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Publications of Author

1. Drew Taussig, Andreas Hoffmann, Achim Nohl, Andrea Kroll
   Application Specific Processing: A Tools Approach. [Citation Graph (0, 0)][DBLP]
   ASAP, 2006, pp:56-64 [Conf]
   
2. Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann
   Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:161-171 [Conf]
   
3. Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
   Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:239-244 [Conf]
   
4. Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
   Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:249-254 [Conf]
   
5. Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
   A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:717-722 [Conf]
   
6. Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
   A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:22-27 [Conf]
   
7. Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
   Instruction encoding synthesis for architecture exploration using hierarchical processor models. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:262-267 [Conf]
   
8. Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
   Processor/Memory Co-Exploration on Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10966-10973 [Conf]
   
9. Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
   Generating production quality software development tools using a machine description language. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:674-678 [Conf]
   
10. Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
    RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:156-160 [Conf]
    
11. Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
    A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1256-1263 [Conf]
    
12. Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
    A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:625-630 [Conf]
    
13. Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr
    Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:57-62 [Conf]
    
14. Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr
    Application specific compiler/architecture codesign: a case study. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:185-193 [Conf]
    
15. Andreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli
    A Methodology and Tooling Enabling Application Specific Processor Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:399-404 [Conf]
    
16. Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
    Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:239-244 [Conf]
    
17. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1625-1639 [Journal]
    
18. Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
    A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1338-1354 [Journal]
    
19. 
    Multicore design is the challenge! what is the solution? [Citation Graph (, )][DBLP]
    
    
20. 
    System prototypes: virtual, hardware or hybrid? [Citation Graph (, )][DBLP]
    
    
21. 
    Programming MPSoC platforms: Road works ahead! [Citation Graph (, )][DBLP]