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Tim Kogel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann
    Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:161-171 [Conf]
  2. Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
    A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:280-285 [Conf]
  3. Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
    A modular simulation framework for architectural exploration of on-chip interconnection networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:7-12 [Conf]
  4. Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
    Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:249-254 [Conf]
  5. Tim Kogel, Heinrich Meyr
    Heterogeneous MP-SoC: the solution to energy-efficient signal processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:686-691 [Conf]
  6. Andreas Hoffmann, Tim Kogel, Heinrich Meyr
    A framework for fast hardware-software co-simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:760-765 [Conf]
  7. Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
    A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1276-1283 [Conf]
  8. Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
    A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:876-881 [Conf]
  9. Tim Kogel, Matthew Braun
    Virtual prototyping of embedded platforms for wireless and multimedia. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:488-490 [Conf]
  10. Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
    A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1256-1263 [Conf]
  11. Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:138-148 [Conf]
  12. Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Early ISS Integration into Network-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:443-452 [Conf]
  13. Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
    A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1338-1354 [Journal]

  14. ESL hand-off: fact or EDA fiction? [Citation Graph (, )][DBLP]

  15. From milliwatts to megawatts: system level power challenge. [Citation Graph (, )][DBLP]

  16. Heterogeneous System-level Specification Using SystemC. [Citation Graph (, )][DBLP]

  17. OCP TLM for Architectural Modelling. [Citation Graph (, )][DBLP]

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