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Yuan Xie: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reliability-Aware Co-Synthesis for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:41-50 [Conf]
  2. John Conner, Yuan Xie, Mahmut T. Kandemir, Robert Dick, Greg M. Link
    FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:709-712 [Conf]
  3. Ozcan Ozturk, Feng Wang 0004, Mahmut T. Kandemir, Yuan Xie
    Optimal topology exploration for application-specific 3D architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:390-395 [Conf]
  4. Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Designing reliable circuit in the presence of soft errors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1- [Conf]
  5. Yuan Xie, Wayne Wolf
    Co-synthesis with custom ASICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:129-134 [Conf]
  6. Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie
    Low-leakage robust SRAM cell design for sub-100nm technologies. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:539-544 [Conf]
  7. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
    FLAW: FPGA lifetime awareness. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:630-635 [Conf]
  8. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:898-899 [Conf]
  9. Chang Hong Lin, Yuan Xie, Wayne Wolf
    LZW-Based Code Compression for VLIW Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:76-81 [Conf]
  10. Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie
    Reliability-Centric High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1258-1263 [Conf]
  11. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:230-231 [Conf]
  12. Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    On-chip bus thermal analysis and optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:850-855 [Conf]
  13. Yuan Xie, Wayne Wolf
    Allocation and scheduling of conditional task graph in hardware/software co-synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:620-625 [Conf]
  14. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Profile-Driven Selective Code Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10462-10467 [Conf]
  15. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
    Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:64-69 [Conf]
  16. Yuan Xie, Haris Lekatsas, Wayne Wolf
    Code Compression for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2001, pp:525- [Conf]
  17. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
    DCC, 2003, pp:382-391 [Conf]
  18. Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Design of a nanosensor array architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:298-303 [Conf]
  19. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
    Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:107-110 [Conf]
  20. W.-L. Hung, Xiaoxia Wu, Yuan Xie
    Guaranteeing performance yield in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:303-309 [Conf]
  21. Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:430-437 [Conf]
  22. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwad, John Conner
    Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:689-696 [Conf]
  23. Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
    Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:677-682 [Conf]
  24. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Three-Dimensional Cache Design Exploration Using 3DCacti. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:519-524 [Conf]
  25. Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
    Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:130-141 [Conf]
  26. Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    The Effect of Threshold Voltages on the Soft Error Rate. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:503-508 [Conf]
  27. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:98-104 [Conf]
  28. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin
    Thermal-Aware Floorplanning Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:634-639 [Conf]
  29. Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung
    Reliability-Centric Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:375-380 [Conf]
  30. Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung
    An ILP Formulation for Reliability-Oriented High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:364-369 [Conf]
  31. Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Variation Analysis of CAM Cells. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:333-338 [Conf]
  32. K. Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Variation Impact on SER of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:911-916 [Conf]
  33. Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
    Modeling of PMOS NBTI Effect Considering Temperature Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:139-144 [Conf]
  34. Haris Lekatsas, Wayne Wolf, Yuan Xie
    Code Compression for VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:138-143 [Conf]
  35. Daniel Hostetler, Yuan Xie
    Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:186-191 [Conf]
  36. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie
    Reliability-Aware SOC Voltage Islands Partition and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:343-348 [Conf]
  37. Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
    Dependability Analysis of Nano-scale FinFET circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:399-404 [Conf]
  38. Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
    Delay and Energy Efficient Data Transmission for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:355-360 [Conf]
  39. Yuan Xie, Wayne Wolf, Haris Lekatsas
    A code decompression architecture for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:66-75 [Conf]
  40. R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:499-502 [Conf]
  41. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
    A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:657-664 [Conf]
  42. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:374-379 [Conf]
  43. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang
    Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:165-170 [Conf]
  44. Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan
    Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:165-170 [Conf]
  45. Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Architecting Microprocessor Components in 3D Design Space. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:103-108 [Conf]
  46. Narayanan Vijaykrishnan, Yuan Xie
    Reliability Concerns in Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2006, v:39, n:1, pp:118-120 [Journal]
  47. Yuan Xie, Jiang Xu, Wayne Wolf
    Augmenting Platform-Based Design with Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:125-142 [Journal]
  48. Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein
    Design space exploration for 3D architectures. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:2, pp:65-103 [Journal]
  49. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:525-536 [Journal]
  50. Feng Wang 0004, Yuan Xie, Hai Ju
    A novel criticality computation method in statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1611-1616 [Conf]
  51. Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
    Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:546-551 [Conf]
  52. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
    A novel dimensionally-decomposed router for on-chip communication in 3D architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:138-149 [Conf]
  53. Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
    A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:160-170 [Conf]
  54. W.-L. Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  55. Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie
    Reliability-Centric High-Level Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  56. Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  57. Gabriel H. Loh, Yuan Xie, Bryan Black
    Processor Design in 3D Die-Stacking Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:31-48 [Journal]
  58. Chang Hong Lin, Yuan Xie, Wayne Wolf
    Code Compression for VLIW Embedded Systems Using a Self-Generating Table. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1160-1171 [Journal]
  59. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Decompression Unit Design for VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:975-980 [Journal]
  60. Yuan Xie, Wei-Lun Hung
    Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:45, n:3, pp:177-189 [Journal]

  61. System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). [Citation Graph (, )][DBLP]


  62. Variation-aware resource sharing and binding in behavioral synthesis. [Citation Graph (, )][DBLP]


  63. Tolerating process variations in high-level synthesis using transparent latches. [Citation Graph (, )][DBLP]


  64. A framework for estimating NBTI degradation of microarchitectural components. [Citation Graph (, )][DBLP]


  65. A criticality-driven microarchitectural three dimensional (3D) floorplanner. [Citation Graph (, )][DBLP]


  66. Variability-driven module selection with joint design time optimization and post-silicon tuning. [Citation Graph (, )][DBLP]


  67. CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. [Citation Graph (, )][DBLP]


  68. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. [Citation Graph (, )][DBLP]


  69. Cost-driven 3D integration with interconnect layers. [Citation Graph (, )][DBLP]


  70. Impact of process variations on emerging memristor. [Citation Graph (, )][DBLP]


  71. Cost-aware three-dimensional (3D) many-core multiprocessor design. [Citation Graph (, )][DBLP]


  72. A Variation Aware High Level Synthesis Framework. [Citation Graph (, )][DBLP]


  73. Power and performance of read-write aware Hybrid Caches with non-volatile memories. [Citation Graph (, )][DBLP]


  74. Gate replacement techniques for simultaneous leakage and aging optimization. [Citation Graph (, )][DBLP]


  75. Energy- and endurance-aware design of phase change memory caches. [Citation Graph (, )][DBLP]


  76. Technology, CAD tools, and designs for emerging 3D integration technology. [Citation Graph (, )][DBLP]


  77. A low-power phase change memory based hybrid cache architecture. [Citation Graph (, )][DBLP]


  78. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. [Citation Graph (, )][DBLP]


  79. Variation-aware task allocation and scheduling for MPSoC. [Citation Graph (, )][DBLP]


  80. Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. [Citation Graph (, )][DBLP]


  81. Thermal-aware reliability analysis for platform FPGAs. [Citation Graph (, )][DBLP]


  82. PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. [Citation Graph (, )][DBLP]


  83. FPGA routing architecture analysis under variations. [Citation Graph (, )][DBLP]


  84. Scan chain design for three-dimensional integrated circuits (3D ICs). [Citation Graph (, )][DBLP]


  85. Comparative analysis of NBTI effects on low power and high performance flip-flops. [Citation Graph (, )][DBLP]


  86. Test-access mechanism optimization for core-based three-dimensional SOCs. [Citation Graph (, )][DBLP]


  87. Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. [Citation Graph (, )][DBLP]


  88. MIRA: A Multi-layered On-Chip Interconnect Router Architecture. [Citation Graph (, )][DBLP]


  89. Hybrid cache architecture with disparate memory technologies. [Citation Graph (, )][DBLP]


  90. Emerging technologies and their impact on system design. [Citation Graph (, )][DBLP]


  91. Low-power dual-element memristor based memory design. [Citation Graph (, )][DBLP]


  92. Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. [Citation Graph (, )][DBLP]


  93. 3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. [Citation Graph (, )][DBLP]


  94. Hierarchical Soft Error Estimation Tool (HSEET). [Citation Graph (, )][DBLP]


  95. On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. [Citation Graph (, )][DBLP]


  96. NBTI-aware statistical circuit delay assessment. [Citation Graph (, )][DBLP]


  97. Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. [Citation Graph (, )][DBLP]


  98. Processor Architecture Design Using 3D Integration Technology. [Citation Graph (, )][DBLP]


  99. Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. [Citation Graph (, )][DBLP]


  100. Leakage Optimized DECAP Design for FPGAs. [Citation Graph (, )][DBLP]


  101. Power optimization for FinFET-based circuits using genetic algorithms. [Citation Graph (, )][DBLP]


  102. ILP-based scheme for timing variation-aware scheduling and resource binding. [Citation Graph (, )][DBLP]


  103. Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. [Citation Graph (, )][DBLP]


  104. Two-dimensional crosstalk avoidance codes. [Citation Graph (, )][DBLP]


  105. Arithmetic unit design using 180nm TSV-based 3D stacking technology. [Citation Graph (, )][DBLP]


  106. 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). [Citation Graph (, )][DBLP]


  107. Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. [Citation Graph (, )][DBLP]


  108. Statistical High-Level Synthesis under Process Variability. [Citation Graph (, )][DBLP]


  109. Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. [Citation Graph (, )][DBLP]


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