The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tong Jing: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
    Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:198-203 [Conf]
  2. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
    DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:618-623 [Conf]
  3. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu, Guiying Yan
    An-OARSMan: obstacle-avoiding routing tree construction with good length performance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:7-12 [Conf]
  4. Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
    A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:115-120 [Conf]
  5. Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong
    CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:630-635 [Conf]
  6. Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
    The polygonal contraction heuristic for rectilinear Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1-6 [Conf]
  7. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:473-478 [Conf]
  8. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
    A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:677-682 [Conf]
  9. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
    Efficient octilinear Steiner tree construction based on spanning graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:687-690 [Conf]
  10. Jingyu Xu, Xianlong Hong, Tong Jing
    Timing-driven global routing with efficient buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2449-2452 [Conf]
  11. Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
    Performance and RLC crosstalk driven global routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:65-68 [Conf]
  12. Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu
    A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:165-168 [Conf]
  13. Zhe Feng 0002, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:48-55 [Conf]
  14. Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
    Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:616-621 [Conf]
  15. Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
    An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:442-452 [Conf]
  16. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:344-353 [Conf]
  17. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:473-478 [Conf]
  18. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An efficient hierarchical timing-driven Steiner tree algorithm for global routing. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:2, pp:69-84 [Journal]
  19. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
    A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:457-473 [Journal]
  20. Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Gu Jun
    CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:6, pp:732-738 [Journal]
  21. Yu Hu, Tong Jing, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan
    ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:1, pp:147-152 [Journal]
  22. Tong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Gu Jun
    SSTT: Efficient Local Search for GSI Global Routing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:5, pp:632-640 [Journal]
  23. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
    UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:358-365 [Journal]
  24. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
    Spanning graph-based nonrectilinear steiner tree algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1066-1075 [Journal]
  25. S. P. Shang, Xiaodong Hu, Tong Jing
    Average lengths of wire routing under M-architecture and X-architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Yu Hu, King Ho Tam, Tong Jing, Lei He
    Fast dual-vdd buffering based on interconnect prediction and sampling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:95-102 [Conf]
  27. Songpu Shang, Xiaodong Hu, Tong Jing
    Rotational Steiner Ratio Problem Under Uniform Orientation Metrics. [Citation Graph (0, 0)][DBLP]
    CJCDGCGT, 2005, pp:166-176 [Conf]

  28. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. [Citation Graph (, )][DBLP]


  29. Temperature aware microprocessor floorplanning considering application dependent power load. [Citation Graph (, )][DBLP]


Search in 0.045secs, Finished in 0.046secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002