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Author:
Xianlong Hong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
    Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:198-203 [Conf]
  2. Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
    Relaxed hierarchical power/ground grid analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1090-1093 [Conf]
  3. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
    DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:618-623 [Conf]
  4. Haiyun Bao, Xianlong Hong, Yici Cai
    A New Global Routing Algorithm Independent Of Net Ordering. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:245-248 [Conf]
  5. Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
    FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:363-0 [Conf]
  6. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    A buffer planning algorithm with congestion optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:615-620 [Conf]
  7. Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu
    VLSI block placement using less flexibility first principles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:601-604 [Conf]
  8. Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong
    A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:453-456 [Conf]
  9. Shuzhou Fang, Zeyi Wang, Xianlong Hong
    A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:305-310 [Conf]
  10. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:505-510 [Conf]
  11. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    VLSI on-chip power/ground network optimization considering decap leakage currents. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:735-738 [Conf]
  12. Jiangchun Gu, Zeyi Wang, Xianlong Hong
    Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:447-452 [Conf]
  13. Jinsong Hou, Zeyi Wang, Xianlong Hong
    The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:93-0 [Conf]
  14. Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
    A new congestion-driven placement algorithm based on cell inflation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:605-608 [Conf]
  15. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu, Guiying Yan
    An-OARSMan: obstacle-avoiding routing tree construction with good length performance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:7-12 [Conf]
  16. Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
    Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:99-102 [Conf]
  17. Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai
    A Timing-Driven Block Placer Based on Sequence Pair Model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:249-252 [Conf]
  18. Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
    A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:115-120 [Conf]
  19. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:582-587 [Conf]
  20. Di Long, Xianlong Hong, Sheqin Dong
    Signal-path driven partition and placement for analog circuit. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:694-699 [Conf]
  21. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:588-593 [Conf]
  22. Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    VLSI floorplanning with boundary constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:509-514 [Conf]
  23. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Buffer allocation algorithm with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:621-623 [Conf]
  24. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:387-392 [Conf]
  25. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
    Efficient early stage resonance estimation techniques for C4 package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:826-831 [Conf]
  26. Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong
    CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:630-635 [Conf]
  27. Renshen Wang, Sheqin Dong, Xianlong Hong
    An improved P-admissible floorplan representation based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1115-1118 [Conf]
  28. Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
    The polygonal contraction heuristic for rectilinear Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1-6 [Conf]
  29. Xiaohai Wu, Changge Qiao, Xianlong Hong
    Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:21-0 [Conf]
  30. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:473-478 [Conf]
  31. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
    A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:677-682 [Conf]
  32. Zhang Yan, Wang Baohua, Yici Cai, Xianlong Hong
    Area routing oriented hierarchical corner stitching with partial bin. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:105-110 [Conf]
  33. Hong Yu, Xianlong Hong, Yici Cai
    MMP: a novel placement algorithm for combined macro block and standard cell layout design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:271-276 [Conf]
  34. Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu
    LFF algorithm for heterogeneous FPGA floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1123-1126 [Conf]
  35. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
    Efficient octilinear Steiner tree construction based on spanning graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:687-690 [Conf]
  36. Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Analysis of buffered hybrid structured clock networks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:93-98 [Conf]
  37. Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
    FARM: An Efficient Feed-Through Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:530-535 [Conf]
  38. Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
    Performance-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:177-181 [Conf]
  39. Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
    An Efficient Timing-Driven Global Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:596-600 [Conf]
  40. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Partitioning-based approach to fast on-chip decap budgeting and minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:170-175 [Conf]
  41. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:176-181 [Conf]
  42. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:806-811 [Conf]
  43. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:770-775 [Conf]
  44. Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
    A New Buffer Planning Algorithm Based on Room Resizing. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:291-299 [Conf]
  45. Rong Liu, Sheqin Dong, Xianlong Hong
    Fixed-outline floorplanning based on common subsequence. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:156-159 [Conf]
  46. Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai
    A new algorithm for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:221-224 [Conf]
  47. Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong
    An improved direct boundary element method for substrate coupling resistance extraction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:84-87 [Conf]
  48. Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
    Improved multilevel routing with redundant via placement for yield and reliability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:143-146 [Conf]
  49. Xinjie Wei, Yici Cai, Xianlong Hong
    Physical aware clock skew rescheduling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:473-476 [Conf]
  50. Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
    An effective buffer planning algorithm for IP based fixed-outline SOC placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:564-569 [Conf]
  51. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
    New timing and routability driven placement algorithms for FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:570-575 [Conf]
  52. Yanming Jia, Yici Cai, Xianlong Hong
    Dummy fill aware buffer insertion during routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:31-36 [Conf]
  53. Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:8-12 [Conf]
  54. Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:153-157 [Conf]
  55. H. Yao, S. Sinha, C. Chiang, X. Hong, Y. Cai
    Efficient process-hotspot detection using range pattern matching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:625-632 [Conf]
  56. Wenjian Yu, Zeyi Wang, Xianlong Hong
    Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:58-63 [Conf]
  57. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
    A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:344-349 [Conf]
  58. Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou
    Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. [Citation Graph (0, 0)][DBLP]
    ICCSA (4), 2005, pp:896-905 [Conf]
  59. Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
    A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:275-286 [Conf]
  60. Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong
    A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. [Citation Graph (0, 0)][DBLP]
    ICNC (3), 2005, pp:181-184 [Conf]
  61. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    Integrated routing resource assignment for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1871-1874 [Conf]
  62. Yici Cai, Yibo Wang, Xianlong Hong
    A global interconnect optimization algorithm under accurate delay model using solution space smoothing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:93-96 [Conf]
  63. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    VLSI block placement with alignment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6222-6225 [Conf]
  64. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Evaluating a bounded slice-line grid assignment in O(nlogn) time. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:708-711 [Conf]
  65. Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu
    Module placement based on quadratic programming and rectangle packing using less flexibility first principle. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:61-64 [Conf]
  66. Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
    Partial random walk for large linear network analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:173-177 [Conf]
  67. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
  68. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Layer assignment algorithm for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:85-88 [Conf]
  69. Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
    Fixed-outline floorplanning with constraints through instance augmentation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1883-1886 [Conf]
  70. Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu
    Algorithms for analog VLSI 2D stack generation and block merging. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:716-719 [Conf]
  71. Di Long, Xianlong Hong, Sheqin Dong
    Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2999-3002 [Conf]
  72. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Performance constrained floorplanning based on partial clustering [IC layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1863-1866 [Conf]
  73. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
    Arbitrary convex and concave rectilinear block packing based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:493-496 [Conf]
  74. Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai
    Combining clustering and partitioning in quadratic placement. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:720-723 [Conf]
  75. Yunfeng Wang, Jinian Bian, Xianlong Hong
    Interconnect delay optimization via high level re-synthesis after floorplanning. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5641-5644 [Conf]
  76. Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
    Algorithm for yield driven correction of layout. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:241-245 [Conf]
  77. Xinjie Wei, Yici Cai, Xianlong Hong
    Zero skew clock routing with tree topology construction using simulated annealing method. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:101-104 [Conf]
  78. Jingyu Xu, Xianlong Hong, Tong Jing
    Timing-driven global routing with efficient buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2449-2452 [Conf]
  79. Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
    Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:81-84 [Conf]
  80. Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
    Crosstalk driven routing resource assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:89-92 [Conf]
  81. Yiqian Zhang, Xianlong Hong, Yici Cai
    An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:97-100 [Conf]
  82. Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
    Performance and RLC crosstalk driven global routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:65-68 [Conf]
  83. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
    Shielding area optimization under the solution of interconnect crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:297-300 [Conf]
  84. Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong
    Quick and effective buffered legitimate skew clock routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:337-340 [Conf]
  85. Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
    A new approach based on LFF for optimization of dynamic hardware reconfigurations. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1210-1213 [Conf]
  86. Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu
    A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:165-168 [Conf]
  87. Zhe Feng 0002, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:48-55 [Conf]
  88. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
    Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:178-185 [Conf]
  89. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    An integrated floorplanning with an efficient buffer planning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:136-142 [Conf]
  90. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
    High accurate pattern based precondition method for extremely large power/ground grid analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:108-113 [Conf]
  91. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:628-633 [Conf]
  92. Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:272-277 [Conf]
  93. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Buffer Planning Algorithm Based on Partial Clustered Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:213-219 [Conf]
  94. Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
    Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:63-68 [Conf]
  95. Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:542-547 [Conf]
  96. Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
    Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:616-621 [Conf]
  97. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
    Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:299-304 [Conf]
  98. Xinjie Wei, Yici Cai, Xianlong Hong
    Clock Skew Scheduling Under Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:237-242 [Conf]
  99. Hongjie Bai, Sheqin Dong, Xianlong Hong
    Congestion Driven Buffer Planning for X-Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:835-840 [Conf]
  100. Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
    Power Delivery Aware Floorplanning for Voltage Island Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:350-355 [Conf]
  101. Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
    Interconnect Power Optimization Based on Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:119-124 [Conf]
  102. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
    Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:383-388 [Conf]
  103. Hailong Yao, Yici Cai, Xianlong Hong
    CMP-aware Maze Routing Algorithm for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:239-244 [Conf]
  104. Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong
    Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
  105. Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
    Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
  106. Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
    A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
  107. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:433-441 [Conf]
  108. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:257-266 [Conf]
  109. Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
    An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:442-452 [Conf]
  110. Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Efficient Simulation of Power/Ground Networks with Package and Vias. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:318-328 [Conf]
  111. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:344-353 [Conf]
  112. Shuzhou Fang, Zeyi Wang, Xianlong Hong
    A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:305-310 [Conf]
  113. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:387-392 [Conf]
  114. Yibo Wang, Yici Cai, Xianlong Hong
    A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:91-96 [Conf]
  115. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:473-478 [Conf]
  116. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with abutment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:65-77 [Journal]
  117. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An efficient hierarchical timing-driven Steiner tree algorithm for global routing. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:2, pp:69-84 [Journal]
  118. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
    A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:457-473 [Journal]
  119. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
    An Optimum Placement Search Algorithm Based on Extended Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:6, pp:699-707 [Journal]
  120. Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong
    Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:224-230 [Journal]
  121. Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong
    Shielding Area Optimization Under the Solution of Interconnect Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:6, pp:901-906 [Journal]
  122. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
    Fast Evaluation of Bounded Slice-Line Grid. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:973-980 [Journal]
  123. Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Gu Jun
    CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:6, pp:732-738 [Journal]
  124. Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu
    Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:6, pp:739-746 [Journal]
  125. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
    FaSa: A Fast and Stable Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:318-324 [Journal]
  126. Yu Hu, Tong Jing, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan
    ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:1, pp:147-152 [Journal]
  127. Tong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Gu Jun
    SSTT: Efficient Local Search for GSI Global Routing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:5, pp:632-640 [Journal]
  128. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
    Crosstalk-Aware Routing Resource Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:231-236 [Journal]
  129. Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    General Floorplans with L/T-Shaped Blocks Using Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:922-926 [Journal]
  130. Yongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong
    Leakage Current Estimation of CMOS Circuit with Stack Effect. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:5, pp:708-717 [Journal]
  131. Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong
    Priority-Based Routing Resource Assignment Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:913-921 [Journal]
  132. Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
    TIGER: an efficient timing-driven global router for gate array and standard cell layout design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1323-1331 [Journal]
  133. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
    UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:358-365 [Journal]
  134. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2402-2412 [Journal]
  135. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
    Buffer planning as an Integral part of floorplanning with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:609-621 [Journal]
  136. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area minimization of power distribution network using efficient nonlinear programming techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1086-1094 [Journal]
  137. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
    Spanning graph-based nonrectilinear steiner tree algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1066-1075 [Journal]
  138. Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
    Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:325-345 [Journal]
  139. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway compaction using corner block list and its applications with rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:199-211 [Journal]
  140. Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Statistical model order reduction for interconnect circuits considering spatial correlations. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1508-1513 [Conf]
  141. Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
    A Fast 3D-BSG Algorithm for 3D Packing Problem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2044-2047 [Conf]
  142. Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
    Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2040-2043 [Conf]
  143. Xinjie Wei, Yici Cai, Xianlong Hong
    Effective Acceleration of Iterative Slack Distribution Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1077-1080 [Conf]
  144. Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou
    Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3411-3414 [Conf]
  145. Yibo Wang, Yici Cai, Xianlong Hong
    Performance and power aware buffered tree construction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  146. Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
    High performance clock routing in X-architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  147. Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
    Buffer planning based on block exchanging. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  148. Sheqin Dong, Shuyi Zheng, Xianlong Hong
    Floorplanning for 2.5-D system integration using multi-layer-BSG structure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  149. Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu
    On handling the fixed-outline constraints of floorplanning using less flexibility first principles. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  150. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong
    A novel low-power physical design methodology for MTCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  151. Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
    A novel technique integrating buffer insertion into timing driven placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  152. Hailong Yao, Yici Cai, Xianlong Hong
    Congestion-driven W-shape multilevel full-chip routing framework. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  153. Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
    An accurate and efficient probabilistic congestion estimation model in x architecture. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:25-32 [Conf]
  154. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
    An efficient quadratic placement based on search space traversing technology. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:253-260 [Journal]
  155. Yaoguang Wei, Sheqin Dong, Xianlong Hong
    APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:406-419 [Journal]
  156. Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Partitioning-based decoupling capacitor budgeting via sequence of linear programming. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:516-524 [Journal]
  157. Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
    A Yield-Driven Gridless Router. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:653-660 [Journal]
  158. Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong
    Legitimate Skew Clock Routing with Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:107-116 [Journal]

  159. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. [Citation Graph (, )][DBLP]


  160. A novel thermal optimization flow using incremental floorplanning for 3D ICs. [Citation Graph (, )][DBLP]


  161. Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. [Citation Graph (, )][DBLP]


  162. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. [Citation Graph (, )][DBLP]


  163. Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. [Citation Graph (, )][DBLP]


  164. Heuristic power/ground network and floorplan co-design method. [Citation Graph (, )][DBLP]


  165. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. [Citation Graph (, )][DBLP]


  166. Logic and Layout Aware Voltage Island Generation for Low Power Design. [Citation Graph (, )][DBLP]


  167. Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. [Citation Graph (, )][DBLP]


  168. Vertical via design techniques for multi-layered P/G networks. [Citation Graph (, )][DBLP]


  169. LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. [Citation Graph (, )][DBLP]


  170. Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP]


  171. Symmetry constraint based on mismatch analysis for analog layout in SOI technology. [Citation Graph (, )][DBLP]


  172. Topological routing to maximize routability for package substrate. [Citation Graph (, )][DBLP]


  173. An efficient decoupling capacitance optimization using piecewise polynomial models. [Citation Graph (, )][DBLP]


  174. MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. [Citation Graph (, )][DBLP]


  175. Multi-objective Floorplanning Based on Fuzzy Logic. [Citation Graph (, )][DBLP]


  176. A novel performance driven power gating based on distributed sleep transistor network. [Citation Graph (, )][DBLP]


  177. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  178. Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. [Citation Graph (, )][DBLP]


  179. Gate planning during placement for gated clock network. [Citation Graph (, )][DBLP]


  180. Leakage power optimization for clock network using dual-Vth technology. [Citation Graph (, )][DBLP]


  181. Diffusion-driven congestion reduction for substrate topological routing. [Citation Graph (, )][DBLP]


  182. Activity and register placement aware gated clock network design. [Citation Graph (, )][DBLP]


  183. Efficient power network analysis with complete inductive modeling. [Citation Graph (, )][DBLP]


  184. IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. [Citation Graph (, )][DBLP]


  185. Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. [Citation Graph (, )][DBLP]


  186. DFM Based Detailed Routing Algorithm for ECP and CMP. [Citation Graph (, )][DBLP]


  187. Simultaneous buffer and interlayer via planning for 3D floorplanning. [Citation Graph (, )][DBLP]


  188. Incremental power optimization for multiple supply voltage design. [Citation Graph (, )][DBLP]


  189. Cell shifting aware of wirelength and overlap. [Citation Graph (, )][DBLP]


  190. A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. [Citation Graph (, )][DBLP]


  191. Full-chip routing system for reducing Cu CMP & ECP variation. [Citation Graph (, )][DBLP]


  192. Integrated interlayer via planning and pin assignment for 3D ICs. [Citation Graph (, )][DBLP]


  193. A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. [Citation Graph (, )][DBLP]


  194. Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. [Citation Graph (, )][DBLP]


  195. DFM-aware Routing for Yield Enhancement. [Citation Graph (, )][DBLP]


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