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Chen-Yi Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuan-Hau Yeh, Chen-Yi Lee
    Buffer size optimization for full-search block matching algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:76-85 [Conf]
  2. Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
    Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:288-289 [Conf]
  3. Cheng-Hsien Chen, Chen-Yi Lee
    A Cost-Effective Lighting Processor for 3D Graphics Application. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1999, pp:792-796 [Conf]
  4. Yew-San Lee, Wei-Shin Chang, Hsin-Han Ho, Chen-Yi Lee
    Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  5. Tsu-Ming Liu, Chen-Yi Lee
    A low-complexity soft vlc decoder using performance modeling. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:3233-3236 [Conf]
  6. Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee
    A high throughput low cost context-based adaptive arithmetic codec for multiple standards. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 2002, pp:872-875 [Conf]
  7. Wen-Shiaw Peng, Chen-Yi Lee
    An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1999, pp:754-758 [Conf]
  8. Hung-Kuo Wei, Yew-San Lee, Yen-Hsu Shih, Chen-Yi Lee
    A novel fixed bit plane error resilient image coding for wireless multimedia transmission. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2002, pp:565-568 [Conf]
  9. Yuan-Hau Yeh, Chen-Yi Lee
    A New Anti-Aliasing Algorithm for Computer Graphics Images. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1999, pp:442-446 [Conf]
  10. Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee
    An area-efficient and high-throughput de-blocking filter for multi-standard video applications. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:1044-1049 [Conf]
  11. Yen-Juan Chao, Chen-Yi Lee
    A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1628-1631 [Conf]
  12. Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
    An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4875-4878 [Conf]
  13. Shi-Chou Juan, Yen-Jean Chao, Chen-Yi Lee
    Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:181-184 [Conf]
  14. Chen-Yi Lee, Shih-Chou Juan, Wen-Wei Yang
    An area-efficient maximum/minimum detection circuit for digital and video signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:223-226 [Conf]
  15. Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee
    An H.264/AVC decoder with 4×4-block level pipeline. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1810-1813 [Conf]
  16. Ting-An Lin, Chen-Yi Lee
    Predictive equalizer design for DVB-T system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:940-943 [Conf]
  17. Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, Chen-Yi Lee
    A memory-efficient deblocking filter for H.264/AVC video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2140-2143 [Conf]
  18. Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Temg-Yin Hsu, Chen-Yi Lee
    Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:149-152 [Conf]
  19. Eddie G. Tzeng, Chen-Yi Lee
    An Efficient Memory Architecture for Motion Estimation Processor Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:712-715 [Conf]
  20. Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, Chen-Yi Lee
    A new motion compensation design for H.264/AVC decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4558-4561 [Conf]
  21. Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
    Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:165-168 [Conf]
  22. Ren-Yang Yang, Chen-Yi Lee
    High-Throughput Data Compressor Designs Using Content Addressable Memory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:147-150 [Conf]
  23. Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, Chen-Yi Lee
    A novel technique for I/Q imbalance and CFO compensation in OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6030-6033 [Conf]
  24. Jin-Jer Jong, Chen-Yi Lee
    A novel structure for portable digitally controlled oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:272-275 [Conf]
  25. Hsie-Chia Chang, Chen-Yi Lee
    An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:649-652 [Conf]
  26. Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee
    A novel subcircuit extraction algorithm by recursive identification scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:491-494 [Conf]
  27. F. S. Tsai, Chen-Yi Lee
    A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:132-135 [Conf]
  28. Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee
    A wideband digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:710-713 [Conf]
  29. Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee
    A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:330-333 [Conf]
  30. Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee
    Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:326-329 [Conf]
  31. Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
    A power and area efficient multi-mode FEC processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:253-256 [Conf]
  32. Cheng-Hung Liu, Bai-Jue Shieh, Chen-Yi Lee
    A low-power group-based VLD design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:337-340 [Conf]
  33. Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee
    A high throughput context-based adaptive arithmetic codec for JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:133-136 [Conf]
  34. Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee
    A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:121-124 [Conf]
  35. Jhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee
    A Design of CMOS Broadband Amplifier With High-Q Active Inductor. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:86-89 [Conf]
  36. Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee
    Infrastructure for Education and Research of SOC/IP in Taiwan. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:150-0 [Conf]
  37. Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, Chen-Yi Lee
    Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding. [Citation Graph (0, 0)][DBLP]
    PCM (2), 2004, pp:521-528 [Conf]
  38. Hsie-Chia Chang, Chen-Yi Lee
    A Low-Power Design for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:159-170 [Journal]
  39. Cheng-Hsien Chen, Chen-Yi Lee
    Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:377-392 [Journal]
  40. Chen-Yi Lee, Francky Catthoor, Hugo De Man
    Efficient VLSI Architectures for a High-Performance Digital Image Communication System. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1990, v:8, n:8, pp:1481-1491 [Journal]
  41. Yew-San Lee, Keng-Khai Ong, Chen-Yi Lee
    Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:2, pp:176-181 [Journal]
  42. Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee
    A high-throughput memory-based VLC decoder with codeword boundary prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:8, pp:1514-1521 [Journal]
  43. Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee
    A new approach of group-based VLC codec system with full table programmability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:2, pp:210-221 [Journal]
  44. Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee
    A low power turbo/Viterbi decoder for 3GPP2 applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:426-430 [Journal]
  45. Cheng-Hsien Chen, Chen-Yi Lee
    Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 2003, v:19, n:7-8, pp:467-479 [Journal]
  46. Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, Chen-Yi Lee
    A New Soft Variable Length Decoder for Wireless Video Transmission. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2007, v:17, n:2, pp:224-236 [Journal]
  47. Yuan-Hau Yeh, Chen-Yi Lee
    Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:345-358 [Journal]

  48. Multi-mode message passing switch networks applied for QC-LDPC decoder. [Citation Graph (, )][DBLP]


  49. A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System. [Citation Graph (, )][DBLP]


  50. An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications. [Citation Graph (, )][DBLP]


  51. A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. [Citation Graph (, )][DBLP]


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