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Publications of Author

1. Yiqun Zhu, Mohammed Benaissa
   Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:360-368 [Conf]
   
2. Tim Good, Mohammed Benaissa
   AES on FPGA from the Fastest to the Smallest. [Citation Graph (0, 0)][DBLP]
   CHES, 2005, pp:427-440 [Conf]
   
3. Wei Ming Lim, M. Benaissa
   Design space exploration of a hardware-software co-designed GF(2^m) galois field processor for forward error correction and cryptography. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2003, pp:53-58 [Conf]
   
4. Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor
   Bit-Serial Dual Basis Systolic Multipliers for GF 2^m. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:2000-2003 [Conf]
   
5. Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa
   A Dual Basis Systolic Divider for GF(2^m). [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:307-310 [Conf]
   
6. M. G. Parker, Mohammed Benaissa
   Fault-Tolerant Linear Convolution using Residue Number Systems. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:441-444 [Conf]
   
7. Yiqun Zhu, Mohammed Benaissa
   A novel ACS scheme for area-efficient Viterbi decoders. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:264-267 [Conf]
   
8. Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor
   GF(2^m) Multiplication and Division Over the Dual Basis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:3, pp:319-327 [Journal]
   
9. M. G. Parker, Mohammed Benaissa
   Modular Arithmetic Using Low Order Redundant Bases. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1997, v:46, n:5, pp:611-616 [Journal]
   
10. Riyaz A. Patel, Mohammed Benaissa, Said Boussakta
    Fast Modulo 2ⁿ - (2^n-2+1) Addition: A New Class of Adder for RNS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:4, pp:572-576 [Journal]
    
11. Tim Good, Mohammed Benaissa
    AES as stream cipher on a small FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. Riyaz A. Patel, Mohammed Benaissa, Said Boussakta
    Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:11, pp:1484-1492 [Journal]
    
13. Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor
    Finite field inversion over the dual basis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:134-137 [Journal]
    
14. 
    A Scalable Block Cipher Design Using Filter Banks and Lifting over Finite Fields. [Citation Graph (, )][DBLP]
    
    
15. 
    Price to Provide RFID Security and Privacy?. [Citation Graph (, )][DBLP]
    
    
16. 
    Low Area Scalable Montgomery Inversion Over GF(2m). [Citation Graph (, )][DBLP]
    
    
17. 
    Efficient Time-Area Scalable ECC Processor Using µ-Coding Technique. [Citation Graph (, )][DBLP]
    
    
18. 
    High-Speed Pipelined EGG Processor on FPGA. [Citation Graph (, )][DBLP]
    
    
19. 
    Limiting Flexibility in Multiplication over GF(2m): A Design Methodology. [Citation Graph (, )][DBLP]
    
    
20. 
    Low Area-Scalable Hardware/Software Co-Design for Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]