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Publications of Author

1. Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
   Design optimization and space minimization considering timing and code size via retiming and unfolding. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:4, pp:173-183 [Journal]
   
2. Meikang Qiu, Kang Zhang, Maolin Huang
   Usability in mobile interface browsing. [Citation Graph (0, 0)][DBLP]
   Web Intelligence and Agent Systems, 2006, v:4, n:1, pp:43-59 [Journal]
   
3. Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
   Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:1641-1646 [Conf]
   
4. Meikang Qiu, Edwin Hsing-Mean Sha
   Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications. [Citation Graph (0, 0)][DBLP]
   HPCC, 2007, pp:156-167 [Conf]
   
5. Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
   Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2007, v:46, n:1, pp:55-73 [Journal]
   
6. 
   Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic Applications. [Citation Graph (, )][DBLP]
   
   
7. 
   Impacts of Inaccurate Information on Resource Allocation for Multi-Core Embedded Systems. [Citation Graph (, )][DBLP]
   
   
8. 
   QoS for Networked Heterogeneous Real-Time Embedded Systems. [Citation Graph (, )][DBLP]
   
   
9. 
   Loop Fusion Technique with Minimal Memory Cost via Retiming. [Citation Graph (, )][DBLP]
   
   
10. 
    ILP optimal scheduling for multi-module memory. [Citation Graph (, )][DBLP]
    
    
11. 
    Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. [Citation Graph (, )][DBLP]
    
    
12. 
    Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. [Citation Graph (, )][DBLP]
    
    
13. 
    Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment. [Citation Graph (, )][DBLP]
    
    
14. 
    Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. [Citation Graph (, )][DBLP]
    
    
15. 
    Energy saving for memory with loop scheduling and prefetching. [Citation Graph (, )][DBLP]
    
    
16. 
    Global Variable Partition with Virtually Shared Scratch Pad Memory to Minimize Schedule Length. [Citation Graph (, )][DBLP]
    
    
17. 
    Multi-sensor Optimal H_infinity Fusion Filters for a Class of Nonlinear Intelligent Systems with Time Delays. [Citation Graph (, )][DBLP]
    
    
18. 
    H_infinitty Synchronization of General Discrete-Time Chaotic Neural Networks with Time Delays. [Citation Graph (, )][DBLP]
    
    
19. 
    Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. [Citation Graph (, )][DBLP]
    
    
20. 
    Key Establishment in Multi-core Parallel Systems. [Citation Graph (, )][DBLP]
    
    
21. 
    Energy Aware Loop Scheduling for High Performance Multi-Module Memory. [Citation Graph (, )][DBLP]
    
    
22. 
    Voltage Assignment for Soft Real-Time Embedded Systems with Continuous Probability Distribution. [Citation Graph (, )][DBLP]
    
    
23. 
    Heterogeneous real-time embedded software optimization considering hardware platform. [Citation Graph (, )][DBLP]
    
    
24. 
    Minimizing Transferred Data for Code Update on Wireless Sensor Network. [Citation Graph (, )][DBLP]
    
    
25. 
    Failure Rate Minimization with Multiple Function Unit Scheduling for Heterogeneous WSNs. [Citation Graph (, )][DBLP]
    
    
26. 
    Jamming ACK Attack to Wireless Networks and a Mitigation Approach. [Citation Graph (, )][DBLP]
    
    
27. 
    Intelligent Search Agent for Internet Computing with Fuzzy Approach. [Citation Graph (, )][DBLP]
    
    
28. 
    Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC. [Citation Graph (, )][DBLP]
    
    
29. 
    Fault Tolerant Data Collection in Heterogeneous Intelligent Monitoring Networks. [Citation Graph (, )][DBLP]
    
    
30. 
    A Discrete Dynamic Voltage and Frequency Scaling Algorithm Based on Task Graph Unrolling for Multiprocessor System. [Citation Graph (, )][DBLP]