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Publications of Author

1. N. Galbiati, G. Ghidini, C. Cremonesi, L. Larcher
   Impact of the As dose in 0.35 mum EEPROM technology: characterization and modeling. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:7, pp:999-1002 [Journal]
   
2. D. Brazzelli, G. Ghidini, C. Riva
   Optimization of WSi₂ by SiH₄ CVD: impact on oxide quality. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:7, pp:1003-1006 [Journal]
   
3. G. Ghidini, D. Brazzelli
   Evaluation methodology of thin dielectrics for non-volatile memory application. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:9-11, pp:1473-1480 [Journal]
   
4. E. Viganò, A. Ghetti, G. Ghidini, A. S. Spinelli
   Post-breakdown characterization in thin gate oxides. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:9-11, pp:1491-1496 [Journal]
   
5. A. Ghetti, D. Brazzelli, A. Benvenuti, G. Ghidini, A. Pavan
   Anomalous gate oxide conduction on isolation edges: analysis and process optimization. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:8, pp:1229-1235 [Journal]
   
6. S. Cimino, A. Cester, A. Paccagnella, G. Ghidini
   Ionising radiation effects on MOSFET drain current. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:8, pp:1247-1251 [Journal]
   
7. G. Ghidini, A. Garavaglia, G. Giusto, A. Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, D. Ielmini
   Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:8, pp:1221-1227 [Journal]
   
8. M. Langenbuch, R. Bottini, M. E. Vitali, G. Ghidini
   In situ steam generation (ISSG) versus standard steam technology: impact on oxide reliability. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2005, v:45, n:5-6, pp:875-878 [Journal]
   
9. G. Ghidini, M. Langenbuch, R. Bottini, D. Brazzelli, A. Ghetti, N. Galbiati, G. Giusto, A. Garavaglia
   Impact of interface and bulk trapped charges on transistor reliability. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2005, v:45, n:5-6, pp:857-860 [Journal]
   
10. G. Ghidini, C. Capolupo, G. Giusto, A. Sebastiani, B. Stragliati, M. Vitali
    Tunnel oxide degradation under pulsed stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1337-1342 [Journal]
    
11. S. Gerardin, A. Griffoni, A. Cester, A. Paccagnella, G. Ghidini
    Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1669-1672 [Journal]
    
12. 
    A semi-distributed localization protocol for wireless sensor and actor networks. [Citation Graph (, )][DBLP]