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Publications of Author

1. Martin Litzenberger, R. Pichler, Scrgey Bychikhin, Dionyz Pogany, E. Gornik, K. Esmark, Harald Gossner
   Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:9-10, pp:1385-1390 [Journal]
   
2. Scrgey Bychikhin, Martin Litzenberger, R. Pichler, Dionyz Pogany, E. Gornik, G. Groos, M. Stecher
   Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:9-10, pp:1501-1506 [Journal]
   
3. Wolfgang Stadler, K. Esmark, Harald Gossner, M. Streibl, M. Wendel, Wolfgang Fichtner, Dionyz Pogany, Martin Litzenberger, E. Gornik
   Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:9-11, pp:1267-1274 [Journal]
   
4. Dionyz Pogany, J. Kuzmik, J. Darmo, Martin Litzenberger, Scrgey Bychikhin, K. Unterrainer, Z. Mozolova, S. Hascik, Tibor Lalinsky, E. Gornik
   Electrical field mapping in InGaP HEMTs and GaAs terahertz emitters using backside infrared OBIC technique. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:9-11, pp:1673-1677 [Journal]
   
5. M. Blaho, Dionyz Pogany, L. Zullino, A. Andreini, E. Gornik
   Experimental and simulation analysis of a BCD ESD protection element under the DC and TLP stress conditions. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:9-11, pp:1281-1286 [Journal]
   
6. V. Dubec, Scrgey Bychikhin, M. Blaho, Dionyz Pogany, E. Gornik, J. Willemen, N. Qu, Wolfgang Wilkening, L. Zullino, A. Andreini
   A dual-beam Michelson interferometer for investigation of trigger dynamics in ESD protection devices under very fast TLP stress. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:9-11, pp:1557-1561 [Journal]
   
7. M. Blaho, Dionyz Pogany, E. Gornik, M. Denison, G. Groos, M. Stecher
   Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:4, pp:545-548 [Journal]
   
8. M. Heer, V. Dubec, M. Blaho, Scrgey Bychikhin, Dionyz Pogany, E. Gornik, M. Denison, M. Stecher, G. Groos
   Automated setup for thermal imaging and electrical degradation study of power DMOS devices. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2005, v:45, n:9-11, pp:1688-1693 [Journal]
   
9. M. Heer, V. Dubec, Scrgey Bychikhin, Dionyz Pogany, E. Gornik, M. Frank, A. Konrad, J. Schulz
   Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:9-11, pp:1591-1596 [Journal]