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V. Huard: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. G. Ribes, S. Bruyère, F. Monsieur, D. Roy, V. Huard
    New insights into the change of voltage acceleration and temperature activation of oxide breakdown. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1211-1214 [Journal]
  2. F. Monsieur, E. Vincent, V. Huard, S. Bruyère, D. Roy, T. Skotnicki, G. Pananakakis, G. Ghibaudo
    On the role of holes in oxide breakdown mechanism in inverted nMOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1199-1202 [Journal]
  3. G. Ribes, S. Bruyère, M. Denais, F. Monsieur, V. Huard, D. Roy, G. Ghibaudo
    Multi-vibrational hydrogen release: Physical origin of Tbd, Qbd power-law voltage dependence of oxide breakdown in ultra-thin gate oxides. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:12, pp:1842-1854 [Journal]
  4. V. Huard, M. Denais, F. Perrier, N. Revil, C. R. Parthasarathy, A. Bravaix, E. Vincent
    A thorough investigation of MOSFETs NBTI degradation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:1, pp:83-98 [Journal]
  5. A. Bravaix, D. Goguenheim, M. Denais, V. Huard, C. R. Parthasarathy, F. Perrier, N. Revil, E. Vincent
    Impacts of the recovery phenomena on the worst-case of damage in DC/AC stressed ultra-thin NO gate-oxide MOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1370-1375 [Journal]
  6. V. Huard, M. Denais, C. R. Parthasarathy
    NBTI degradation: From physical mechanisms to modelling. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:1, pp:1-23 [Journal]
  7. C. R. Parthasarathy, M. Denais, V. Huard, G. Ribes, D. Roy, C. Guérin, F. Perrier, E. Vincent, A. Bravaix
    Designing in reliability in advanced CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1464-1471 [Journal]
  8. C. R. Parthasarathy, A. Bravaix, C. Guérin, M. Denais, V. Huard
    Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:191-200 [Conf]

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