The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

A. Garavaglia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. G. Ghidini, A. Garavaglia, G. Giusto, A. Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, D. Ielmini
    Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1221-1227 [Journal]
  2. G. Ghidini, M. Langenbuch, R. Bottini, D. Brazzelli, A. Ghetti, N. Galbiati, G. Giusto, A. Garavaglia
    Impact of interface and bulk trapped charges on transistor reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:5-6, pp:857-860 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002