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Hiroto Yasuura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroto Yasuura
    On Parallel Computational Complexity of Unification. [Citation Graph (3, 0)][DBLP]
    FGCS, 1984, pp:235-243 [Conf]
  2. Sozo Inoue, Hiroto Yasuura, Daisuke Hagiwara
    Systematic Error Detection for RFID Reliability. [Citation Graph (0, 0)][DBLP]
    ARES, 2006, pp:280-286 [Conf]
  3. Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
    One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:653-654 [Conf]
  4. Tohru Ishihara, Hiroto Yasuura
    Power-Pro: Programmable Power Management Architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:321-322 [Conf]
  5. Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara
    A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:268-273 [Conf]
  6. Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura
    A variation-aware low-power coding methodology for tightly coupled buses. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:557-560 [Conf]
  7. Makoto Sugihara, Hiroto Yasuura
    Optimization of Test Accesses with a Combined BIST and External Test Scheme. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:683-688 [Conf]
  8. Hiroyuki Tomiyama, Hiroto Yasuura
    Module Selection Using Manufacturing Information. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:275-281 [Conf]
  9. Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino
    A HW/SW co-design environment for multi-media equipments development using inverse problem. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:153-160 [Conf]
  10. Hiroto Yasuura
    Locally Computable Coding for Unary Operations. [Citation Graph (0, 0)][DBLP]
    Concurrency: Theory, Language, And Architecture, 1989, pp:312-323 [Conf]
  11. Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura
    Design Reuse: Fact or Fiction? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:562- [Conf]
  12. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
    NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:8-13 [Conf]
  13. Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
    Memory-CPU Size Optimization for Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:246-251 [Conf]
  14. Hiroto Yasuura, Nagisa Ishiura
    Semantics of a Hardware Design Language for Japanese Standardization. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:836-839 [Conf]
  15. Kei Hirose, Hiroto Yasuura
    A Bus Delay Reduction Technique Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:441-445 [Conf]
  16. Tohru Ishihara, Hiroto Yasuura
    A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:617-616 [Conf]
  17. Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
    Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:134-140 [Conf]
  18. Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
    Instruction Scheduling for Power Reduction in Processor-Based System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:855-860 [Conf]
  19. Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
    A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:210-217 [Conf]
  20. Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura
    A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:408-415 [Conf]
  21. Hiroto Yasuura
    Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:17-22 [Conf]
  22. Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
    An FPGA-based genetic algorithm machine (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:218- [Conf]
  23. Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
    Routing methodology for minimizing 1nterconnect energy dissipation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:120-123 [Conf]
  24. M. Ohmura, Hiroto Yasuura, Keikichi Tamaru
    Extraction of Functional Information from Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:176-179 [Conf]
  25. Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura
    A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:308-317 [Conf]
  26. Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
    Design of data-path module generators from algorithmic representations. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:183-192 [Conf]
  27. Yun Cao, Hiroto Yasuura
    A system-level energy minimization approach using datapath width optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:231-236 [Conf]
  28. Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
    A low-power digital matched filter for spread-spectrum systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:301-306 [Conf]
  29. Tohru Ishihara, Hiroto Yasuura
    Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:117-120 [Conf]
  30. Tohru Ishihara, Hiroto Yasuura
    Voltage scheduling problem for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:197-202 [Conf]
  31. Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura
    Reducing access energy of on-chip data memory considering active data bitwidth. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:88-91 [Conf]
  32. Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
    Power analysis techniques for SoC with improved wiring models. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:259-262 [Conf]
  33. Hiroto Yasuura
    Digitally Named World: Challenges for New Social Infrastructures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:323- [Conf]
  34. Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
    Real-Time Task Scheduling for a Variable Voltage Processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:24-29 [Conf]
  35. Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura
    Instruction Encoding Techniques for Area Minimization of Instruction ROM. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:125-130 [Conf]
  36. Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura
    Statistical Performance-Driven Module Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:66-71 [Conf]
  37. Hiroyuki Tomiyama, Hiroto Yasuura
    Size-Constrained Code Placement for Cache Miss Rate Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:96-104 [Conf]
  38. Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
    An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:32-37 [Conf]
  39. Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao
    Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:201-206 [Conf]
  40. Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
    Special Session: Security on SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:192-194 [Conf]
  41. Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
    A novel test methodology for core-based system LSIs and a testing time minimization problem. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:465-0 [Conf]
  42. Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
    Toward Unlinkable ID Management for Multi-Service Environments. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2005, pp:115-119 [Conf]
  43. Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
    On Authentication between Human and Computer. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2006, pp:636-639 [Conf]
  44. Shuzo Yajima, Hiroto Yasuura
    Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. [Citation Graph (0, 0)][DBLP]
    RIMS Symposium on Software Science and Engineering, 1982, pp:147-164 [Conf]
  45. Hiroto Yasuura, Shuzo Yajima
    Hardware Algorithms for VLSI Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Engineering, 1984, pp:105-129 [Conf]
  46. Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
    A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:268-273 [Conf]
  47. Makoto Sugihara, Hiroto Yasuura
    Optimization of Test Accesses with a Combined BIST and External Test Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:683-688 [Conf]
  48. Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura
    Quantitative evaluation of unlinkable ID matching schemes. [Citation Graph (0, 0)][DBLP]
    WPES, 2005, pp:55-60 [Conf]
  49. Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
    Software Energy Reduction Techniques for Variable-Voltage Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:31-41 [Journal]
  50. Tetsuya Yamada, Hiroto Yasuura
    On the Computational Power of Binary Decision Diagram with Redundant Variables. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1996, v:8, n:1, pp:65-89 [Journal]
  51. Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura
    A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2001, v:2, n:1, pp:33-60 [Journal]
  52. Hiroto Yasuura
    Width and Depth of Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1981, v:13, n:4/5, pp:191-194 [Journal]
  53. Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar
    Embedded System Design Using Soft-Core Processor and Valen-C. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:587-603 [Journal]
  54. Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima
    High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:9, pp:789-796 [Journal]
  55. Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
    The Parallel Enumeration Sorting Scheme for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:12, pp:1192-1201 [Journal]
  56. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
    High-Speed Logic Simulation on Vector Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:305-321 [Journal]
  57. Hiroyuki Tomiyama, Hiroto Yasuura
    Code placement techniques for cache miss rate reduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:410-429 [Journal]
  58. Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
    Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:951-954 [Journal]

  59. A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. [Citation Graph (, )][DBLP]

  60. An Information Platform for Low-Literate Villagers. [Citation Graph (, )][DBLP]

  61. Dependable VLSI: device, design and architecture: how should they cooperate? [Citation Graph (, )][DBLP]

  62. A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. [Citation Graph (, )][DBLP]

  63. Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. [Citation Graph (, )][DBLP]

  64. An Energy Characterization Framework for Software-Based Embedded Systems. [Citation Graph (, )][DBLP]

  65. Simultaneous optimization of memory configuration and code allocation for low power embedded systems. [Citation Graph (, )][DBLP]

  66. An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. [Citation Graph (, )][DBLP]

  67. A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. [Citation Graph (, )][DBLP]

  68. A Door Access Control System with Mobile Phones. [Citation Graph (, )][DBLP]

  69. Signal probability control for relieving NBTI in SRAM cells. [Citation Graph (, )][DBLP]

  70. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. [Citation Graph (, )][DBLP]

  71. Modeling Costs of Access Control with Various Key Management Systems. [Citation Graph (, )][DBLP]

  72. Unlinkability and Real World Constraints in RFID Systems. [Citation Graph (, )][DBLP]

  73. A Note on Biometrics-based Authentication with Portable Device. [Citation Graph (, )][DBLP]

  74. Large Scale Business-academia Collaboration in Master Education Course. [Citation Graph (, )][DBLP]

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