The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sumio Morioka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
    A Compact Rijndael Hardware Architecture with S-Box Optimization. [Citation Graph (0, 0)][DBLP]
    ASIACRYPT, 2001, pp:239-254 [Conf]
  2. Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane
    Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:465-477 [Conf]
  3. Sumio Morioka, Akashi Satoh
    An Optimized S-Box Circuit Architecture for Low Power AES Design. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:172-186 [Conf]
  4. Akashi Satoh, Sumio Morioka
    Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:304-318 [Conf]
  5. Yasunao Katayama, Yasushi Negishi, Sumio Morioka
    Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:201-0 [Conf]
  6. Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu
    Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:311-318 [Conf]
  7. Yasunao Katayama, Sumio Morioka
    One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2000, pp:390-0 [Conf]
  8. Sumio Morioka, Yasunao Katayama
    Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:60-67 [Conf]
  9. Sumio Morioka, Akashi Satoh
    A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:98-103 [Conf]
  10. Akashi Satoh, Sumio Morioka
    Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. [Citation Graph (0, 0)][DBLP]
    ISC, 2002, pp:48-62 [Conf]
  11. Akashi Satoh, Sumio Morioka
    Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. [Citation Graph (0, 0)][DBLP]
    ISC, 2003, pp:252-266 [Conf]
  12. Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi
    Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:165-184 [Conf]
  13. Sumio Morioka, Akashi Satoh
    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:686-691 [Journal]

Search in 0.208secs, Finished in 0.209secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002