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Paritosh K. Pandya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore
    Timed Modelling and Analysis in Web Service Compositions. [Citation Graph (0, 0)][DBLP]
    ARES, 2006, pp:840-846 [Conf]
  2. Gaurav Chakravorty, Paritosh K. Pandya
    Digitizing Interval Duration Logic. [Citation Graph (0, 0)][DBLP]
    CAV, 2003, pp:167-179 [Conf]
  3. Paritosh K. Pandya
    Some Extensions to Propositional Mean-Value Caculus: Expressiveness and Decidability. [Citation Graph (0, 0)][DBLP]
    CSL, 1995, pp:434-451 [Conf]
  4. M. R. K. Krishna Rao, Paritosh K. Pandya, R. K. Shyamasundar
    Verification Tools in the Development of Provably Correct Compilers. [Citation Graph (0, 0)][DBLP]
    FME, 1993, pp:442-461 [Conf]
  5. Kamal Lodaya, Paritosh K. Pandya
    A Dose of Timed Logic, in Guarded Measure. [Citation Graph (0, 0)][DBLP]
    FORMATS, 2006, pp:260-273 [Conf]
  6. Shankara Narayanan Krishna, Paritosh K. Pandya
    Modal Strength Reduction in Quantified Discrete Duration Calculus. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 2005, pp:444-456 [Conf]
  7. K. Narayan Kumar, Paritosh K. Pandya
    ICSP and Its Relationship with ACSP and CSP. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1993, pp:358-372 [Conf]
  8. K. Narayan Kumar, Paritosh K. Pandya
    On the Computational Power of Operators in ICSP with Fairness. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1994, pp:231-242 [Conf]
  9. Paritosh K. Pandya, Y. S. Ramakrishna
    Recursive Mean-Value Calculus. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1998, pp:257-268 [Conf]
  10. Paritosh K. Pandya
    Weak Chop Inverses and Liveness in Mean-Value Calculus. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1996, pp:148-167 [Conf]
  11. Paritosh K. Pandya, Dang Van Hung
    Duration Calculus of Weakly Monotonic Time. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1998, pp:55-64 [Conf]
  12. Manoranjan Satpathy, Dang Van Hung, Paritosh K. Pandya
    Some Decidability Results for Duration Calculus under Synchronous Interpretation. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1998, pp:186-197 [Conf]
  13. Huiqun Yu, Paritosh K. Pandya, Yongqiang Sun
    A Calculus for Hybrid Sampled Data Systems. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1994, pp:716-737 [Conf]
  14. Xinyao Yu, Ji Wang, Chaochen Zhou, Paritosh K. Pandya
    Formal Design of Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1994, pp:738-755 [Conf]
  15. Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore
    Representation, Verification, and Computation of Timed Properties in Web. [Citation Graph (0, 0)][DBLP]
    ICWS, 2006, pp:497-504 [Conf]
  16. Jonathan P. Bowen, Jifeng He, Paritosh K. Pandya
    An Approach to Verifiable Compiling Specification and Prototyping. [Citation Graph (0, 0)][DBLP]
    PLILP, 1990, pp:45-59 [Conf]
  17. Paritosh K. Pandya, H.-P. Wang, Qiwen Xu
    Toward a theory of sequential hybrid programs. [Citation Graph (0, 0)][DBLP]
    PROCOMET, 1998, pp:366-384 [Conf]
  18. Paritosh K. Pandya
    Some Comments on the Assumption-Commitment Framework for Compositional Verification of Distributed Programs. [Citation Graph (0, 0)][DBLP]
    REX Workshop, 1989, pp:622-640 [Conf]
  19. Paritosh K. Pandya
    Model Checking CTL*[DC]. [Citation Graph (0, 0)][DBLP]
    TACAS, 2001, pp:559-573 [Conf]
  20. Babita Sharma, Paritosh K. Pandya, Supratik Chakraborty
    Bounded Validity Checking of Interval Duration Logic. [Citation Graph (0, 0)][DBLP]
    TACAS, 2005, pp:301-316 [Conf]
  21. Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya
    Efficient Guided Symbolic Reachability Using Reachability Expressions. [Citation Graph (0, 0)][DBLP]
    TACAS, 2006, pp:120-134 [Conf]
  22. K. Narayan Kumar, Paritosh K. Pandya
    Infinitary Parallelism without Unbounded Nondeterminism in CSP. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1993, v:30, n:5, pp:467-487 [Journal]
  23. Mathai Joseph, Paritosh K. Pandya
    Finding Response Times in a Real-Time System. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1986, v:29, n:5, pp:390-395 [Journal]
  24. Paritosh K. Pandya, Mathai Joseph
    A Structure-Directed Total Correctness Proof Rule for Recursive Procedure Calls. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1986, v:29, n:6, pp:531-537 [Journal]
  25. Paritosh K. Pandya, Mathai Joseph
    P - A Logic - A Compositional Proof System for Distributed Programs. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1991, v:5, n:, pp:37-54 [Journal]
  26. Paritosh K. Pandya
    The Saga of Synchronous Bus Arbiter: On Model Checking Quantitative Timing Properties of Synchronous Programs. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:65, n:5, pp:- [Journal]
  27. Paritosh K. Pandya
    Interval Duration Logic: Expressiveness and Decidability. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal]
  28. Paritosh K. Pandya
    Finding Extremal Models of Discrete Duration Calculus formulae using Symbolic Search. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:128, n:6, pp:247-262 [Journal]
  29. Paul H. B. Gardiner, Paritosh K. Pandya
    Reasoning Algebraically about Recursion. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 1992, v:18, n:3, pp:271-280 [Journal]
  30. Michael R. Hansen, Paritosh K. Pandya, Zhou Chaochen
    Finite Divergence. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1995, v:138, n:1, pp:113-139 [Journal]
  31. Paritosh K. Pandya, Shankara Narayanan Krishna, Kuntal Loya
    On Sampling Abstraction of Continuous Time Logic with Durations. [Citation Graph (0, 0)][DBLP]
    TACAS, 2007, pp:246-260 [Conf]

  32. Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. [Citation Graph (, )][DBLP]


  33. Around Dot Depth Two. [Citation Graph (, )][DBLP]


  34. Timed Automata with Integer Resets: Language Inclusion and Expressiveness. [Citation Graph (, )][DBLP]


  35. Marking the chops: an unambiguous temporal logic. [Citation Graph (, )][DBLP]


  36. Timed and Hybrid Automata in SAL. [Citation Graph (, )][DBLP]


  37. Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions. [Citation Graph (, )][DBLP]


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