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Publications of Author

1. Gerd Ritter, Holger Hinrichsen, Hans Eveking
   Formal Verification of Descriptions with Distinct Order of Memory Operations. [Citation Graph (0, 0)][DBLP]
   ASIAN, 1999, pp:308-321 [Conf]
   
2. Hans Eveking
   Automatic Verification of Extensions of Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
   CAV, 1990, pp:2-12 [Conf]
   
3. Gerd Ritter, Hans Eveking, Holger Hinrichsen
   Formal Verification of Designs with Complex Control by Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
   CHARME, 1999, pp:234-249 [Conf]
   
4. Hans Eveking, Stefan Höreth
   Optimization and Resynthesis of Complex Data-Paths. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:637-641 [Conf]
   
5. Hans Eveking, Holger Hinrichsen, Gerd Ritter
   Automatic Verification of Scheduling Results in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:59-64 [Conf]
   
6. Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler
   Multi-Level Assertion-Based Design. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2007, pp:85-86 [Conf]
   
7. 
   (V)HDL-based verification of heterogeneous synchronous/asynchronous systems. [Citation Graph (, )][DBLP]
   
   
8. 
   Formal verification of timing conditions. [Citation Graph (, )][DBLP]
   
   
9. 
   A Quantitative Completeness Analysis for Property-Sets. [Citation Graph (, )][DBLP]
   
   
10. 
    A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set. [Citation Graph (, )][DBLP]
    
    
11. 
    On Consistency and Completeness of Property-Sets. [Citation Graph (, )][DBLP]