Doron Drusinsky Automatic Simulation of Network Problems in UDP-Based Java Programs Temporal Logic and Natural Language Conditioned Transitions. [Citation Graph (0, 0)][DBLP] IPDPS, 2004, pp:- [Conf]
Doron Drusinsky, Man-tak Shing Verification of Timing Properties in Rapid System Prototyping. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2003, pp:47-0 [Conf]
Doron Drusinsky, Man-tak Shing TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2004, pp:29-36 [Conf]
Doron Drusinsky On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata. [Citation Graph (0, 0)][DBLP] J. UCS, 2006, v:12, n:5, pp:482-498 [Journal]
Doron Drusinsky, David Harel Using statecharts for hardware description and synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:798-807 [Journal]
Doron Drusinsky, Man-tak Shing Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2007, pp:82-88 [Conf]
Using UML Statecharts with Knowledge Logic Guards. [Citation Graph (, )][DBLP]
Removing the Boundaries: Steps Toward a Cloud Nirvana. [Citation Graph (, )][DBLP]
A design pattern for using non-developmental items in real-time Java. [Citation Graph (, )][DBLP]
Validating UML Statechart-Based Assertions Libraries for Improved Reliability and Assurance. [Citation Graph (, )][DBLP]
Creating and Validating Embedded Assertion Statecharts. [Citation Graph (, )][DBLP]
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