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Gokhan Memik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. G. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik
    Compiler-directed selective data protection against soft errors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:713-716 [Conf]
  2. Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee
    Automatic extraction of function bodies from software binaries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:928-931 [Conf]
  3. Gokhan Memik, William H. Mangione-Smith
    Increasing power efficiency of multi-core network processors through data filtering. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:108-116 [Conf]
  4. Gokhan Memik, William H. Mangione-Smith
    A flexible accelerator for layer 7 networking applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:646-651 [Conf]
  5. Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun
    Global resource sharing for synthesis of control data flow graphs on FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:604-609 [Conf]
  6. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Temperature-aware resource allocation and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:196-201 [Conf]
  7. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif
    An Integrated Approach for Improving Cache Behavior. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10796-10801 [Conf]
  8. Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk
    Increasing Register File Immunity to Transient Errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:586-591 [Conf]
  9. Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
    Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:770-779 [Conf]
  10. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary
    Design and Evaluation of a Compiler-Directed Collective I/O Technique. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1263-1272 [Conf]
  11. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary
    Exploiting Inter-File Access Patterns Using Multi-Collective I/O. [Citation Graph (0, 0)][DBLP]
    FAST, 2002, pp:245-258 [Conf]
  12. Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith
    Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:131-0 [Conf]
  13. David T. Nguyen, Gokhan Memik, Alok N. Choudhary
    A reconfigurable architecture for network intrusion detection using principal component analysis. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:235- [Conf]
  14. David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary
    Real-Time Feature Extraction for High Speed Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:438-443 [Conf]
  15. David Nguyen, Joseph Zambreno, Gokhan Memik
    Flow Monitoring in High-Speed Networks with 2D Hash Tables. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1093-1097 [Conf]
  16. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Power density minimization for highly-associative caches in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:100-104 [Conf]
  17. Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik
    Load elimination for low-power embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:282-285 [Conf]
  18. Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
    Just Say No: Benefits of Early Cache Miss Determinatio. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:307-316 [Conf]
  19. Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary
    JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:85-96 [Conf]
  20. Gokhan Memik, William H. Mangione-Smith, Wendong Hu
    NetBench: A Benchmarking Suite for Network Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:39-0 [Conf]
  21. Yongxiang Liu, Gokhan Memik, Glenn Reinman
    Reducing the Energy of Speculative Instruction Schedulers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:641-646 [Conf]
  22. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary
    Design and Evaluation of Smart Disk Architecture for DSS Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:335-0 [Conf]
  23. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman
    Scaling the issue window with look-ahead latency prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:217-226 [Conf]
  24. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman
    Tornado warning: the perils of selective replay in multithreaded processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:51-60 [Conf]
  25. Xiaohui Shen, Wei-keng Liao, Alok N. Choudhary, Gokhan Memik, Mahmut T. Kandemir, Sachin More, George K. Thiruvathukal, Arti Singh
    A novel application development environment for large-scale scientific computations. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:274-283 [Conf]
  26. Arindam Mallik, Matthew C. Wildrick, Gokhan Memik
    Design and implementation of correlating caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:58-61 [Conf]
  27. Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
    Reducing energy and delay using efficient victim caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:262-265 [Conf]
  28. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Peak temperature control and leakage reduction during binding in high level synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:251-256 [Conf]
  29. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:283-293 [Conf]
  30. Arindam Mallik, Gokhan Memik
    A Case for Clumsy Packet Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:147-156 [Conf]
  31. Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
    Yield-Aware Cache Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:15-25 [Conf]
  32. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Valerie E. Taylor
    APRIL: A Run-Time Library for Tape-Resident Data. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Mass Storage Systems, 2000, pp:61-74 [Conf]
  33. Alok N. Choudhary, Mahmut T. Kandemir, Jaechun No, Gokhan Memik, Xiaohui Shen, Wei-keng Liao, Harsha S. Nagesh, Sachin More, Valerie E. Taylor, Rajeev Thakur, Rick L. Stevens
    Data management for large-scale scientific computations in high performance distributed systems. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2000, v:3, n:1, pp:45-60 [Journal]
  34. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary
    Design and Evaluation of a Smart Disk Cluster for DSS Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:11, pp:1633-1664 [Journal]
  35. Gokhan Memik, William H. Mangione-Smith
    Evaluating Network Processors using NetBench. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:453-471 [Journal]
  36. Gokhan Memik, Mahmut T. Kandemir, Wei-keng Liao, Alok N. Choudhary
    Multicollective I/O: A technique for exploiting inter-file access patterns. [Citation Graph (0, 0)][DBLP]
    TOS, 2006, v:2, n:3, pp:349-369 [Journal]
  37. Zhuan Ye, John Grosspietsch, Gokhan Memik
    Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:21-26 [Conf]
  38. Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
    Interactive presentation: An FPGA implementation of decision tree classification. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:189-194 [Conf]
  39. Ramanathan Narayanan, Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
    Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (3), 2007, pp:734-741 [Conf]
  40. Robert T. Schweller, Zhichun Li, Yan Chen, Yan Gao, Ashish Gupta, Yin Zhang, Peter A. Dinda, Ming-Yang Kao, Gokhan Memik
    Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2006, pp:- [Conf]
  41. Bin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick
    Power reduction through measurement and modeling of users and CPUs: summary. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:363-364 [Conf]
  42. Ramanathan Narayanan, Berkin Özisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
    MineBench: A Benchmark Suite for Data Mining Workloads. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:182-188 [Conf]
  43. Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
    An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:61-70 [Conf]
  44. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:592-604 [Journal]
  45. Arindam Mallik, Gokhan Memik
    Low Power Correlating Caches for Network Processors. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:108-118 [Journal]

  46. PICSEL: measuring user-perceived performance to control dynamic frequency scaling. [Citation Graph (, )][DBLP]


  47. A power and temperature aware DRAM architecture. [Citation Graph (, )][DBLP]


  48. Efficient system design space exploration using machine learning techniques. [Citation Graph (, )][DBLP]


  49. Selective wordline voltage boosting for caches to manage yield under process variations. [Citation Graph (, )][DBLP]


  50. Quantifying and coping with parametric variations in 3D-stacked microarchitectures. [Citation Graph (, )][DBLP]


  51. An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. [Citation Graph (, )][DBLP]


  52. Detecting/preventing information leakage on the memory bus due to malicious hardware. [Citation Graph (, )][DBLP]


  53. Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. [Citation Graph (, )][DBLP]


  54. Sonar-based measurement of user presence and attention. [Citation Graph (, )][DBLP]


  55. Evaluating voltage islands in CMPs under process variations. [Citation Graph (, )][DBLP]


  56. Machine Learning Models to Predict Performance of Computer System Design Alternatives. [Citation Graph (, )][DBLP]


  57. An approach for adaptive DRAM temperature and power management. [Citation Graph (, )][DBLP]


  58. Firefly: illuminating future network-on-chip with nanophotonics. [Citation Graph (, )][DBLP]


  59. Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. [Citation Graph (, )][DBLP]


  60. User- and process-driven dynamic voltage and frequency scaling. [Citation Graph (, )][DBLP]


  61. Analyzing the impact of on-chip network traffic on program phases for CMPs. [Citation Graph (, )][DBLP]


  62. Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures. [Citation Graph (, )][DBLP]


  63. Power to the people: Leveraging human physiological traits to control microprocessor frequency. [Citation Graph (, )][DBLP]


  64. Evaluating the effects of cache redundancy on profit. [Citation Graph (, )][DBLP]


  65. Variable latency caches for nanoscale processor. [Citation Graph (, )][DBLP]


  66. Characterizing and modeling user activity on smartphones: summary. [Citation Graph (, )][DBLP]


  67. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. [Citation Graph (, )][DBLP]


  68. Automated task distribution in multicore network processors using statistical analysis. [Citation Graph (, )][DBLP]


  69. Exploring concentration and channel slicing in on-chip network router. [Citation Graph (, )][DBLP]


  70. The user in experimental computer systems research. [Citation Graph (, )][DBLP]


  71. Energy Detection Using Estimated Noise Variance for Spectrum Sensing in Cognitive Radio Networks. [Citation Graph (, )][DBLP]


  72. Spectrum Sensing Using Cyclostationary Spectrum Density for Cognitive Radios. [Citation Graph (, )][DBLP]


  73. User-Driven Frequency Scaling. [Citation Graph (, )][DBLP]


  74. Microarchitectures for Managing Chip Revenues under Process Variations. [Citation Graph (, )][DBLP]


  75. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education [Citation Graph (, )][DBLP]


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