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Feihui Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Guilin Chen, Mahmut T. Kandemir, Feihui Li
    Energy-aware computation duplication for improving reliability in embedded chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:134-139 [Conf]
  2. Guangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran
    Increasing FPGA resilience against soft errors using task duplication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:924-927 [Conf]
  3. Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
    Prefetching-aware cache line turnoff for saving leakage energy. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:182-187 [Conf]
  4. Mahmut T. Kandemir, Guangyu Chen, Feihui Li
    Maximizing data reuse for minimizing memory space requirements and execution cycles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:808-813 [Conf]
  5. Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran
    Using data replication to reduce communication energy on chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:769-772 [Conf]
  6. Sri Hari Krishna Narayanan, Seung Woo Son, Mahmut T. Kandemir, Feihui Li
    Using loop invariants to fight soft errors in data caches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1317-1320 [Conf]
  7. Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, Feihui Li
    Energy savings through embedded processing on disk system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:128-133 [Conf]
  8. Priya Unnikrishnan, Mahmut T. Kandemir, Feihui Li
    Reducing dynamic compilation overhead by overlapping compilation and execution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:929-934 [Conf]
  9. Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed proactive power management for networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:137-146 [Conf]
  10. Feihui Li, Guilin Chen, Mahmut T. Kandemir, R. R. Brooks
    A Compiler-Based Approach to Data Security. [Citation Graph (0, 0)][DBLP]
    CC, 2005, pp:188-203 [Conf]
  11. Feihui Li, Mahmut T. Kandemir
    Locality-conscious workload assignment for array-based computations in MPSOC architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:95-100 [Conf]
  12. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-Directed Instruction Duplication for Soft Error Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1056-1057 [Conf]
  13. Mahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu
    Activity clustering for leakage management in SPMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:696-697 [Conf]
  14. Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangyu Chen, Ozcan Ozturk
    Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1026-1031 [Conf]
  15. Liping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu
    Dynamic partitioning of processing and memory resources in embedded MPSoC architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:690-695 [Conf]
  16. Feihui Li, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy
    Exploiting last idle periods of links for network power management. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:134-137 [Conf]
  17. Feihui Li, Guilin Chen, Mahmut T. Kandemir
    Compiler-directed voltage scaling on communication links for reducing power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:456-460 [Conf]
  18. Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ibrahim Kolcu
    Improving scratch-pad memory reliability through compiler-guided data block duplication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1002-1005 [Conf]
  19. Feihui Li, Mahmut T. Kandemir
    Improving Performance of Java Applications Using a Coprocessor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  20. Feihui Li, Pyush Agrawal, Grace Eberhardt, Eren Manavoglu, Secil Ugurel, Mahmut T. Kandemir
    Improving Memory Performance of Embedded Java Applications by Dynamic Layout Modifications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  21. Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
    Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:130-141 [Conf]
  22. Feihui Li, Mahmut T. Kandemir
    Increasing Data TLB Resilience to Transient Errors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:297-298 [Conf]
  23. Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran
    Compiler-Directed Management of Leakage Power in Software-Managed Memories. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:450-451 [Conf]
  24. Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu
    Exploiting Software Pipelining for Network-on-Chip architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:295-302 [Conf]
  25. Feihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu
    Leakage-Aware SPM Management. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:393-398 [Conf]
  26. Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed thermal management for VLIW functional units. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:163-172 [Conf]
  27. Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin
    Reducing NoC energy consumption through compiler-directed channel voltage scaling. [Citation Graph (0, 0)][DBLP]
    PLDI, 2006, pp:193-203 [Conf]
  28. Guangyu Chen, Feihui Li, Mahmut T. Kandemir
    Compiler-directed channel allocation for saving power in on-chip networks. [Citation Graph (0, 0)][DBLP]
    POPL, 2006, pp:194-205 [Conf]
  29. Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, R. Ramanarayanan, Balaji Vaidyanathan
    A Process Scheduler-Based Approach to NoC Power Management. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:77-82 [Conf]
  30. Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, R. Ramanarayanan, Balaji Vaidyanathan
    Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:251-258 [Conf]
  31. Guangyu Chen, Feihui Li, Mahmut T. Kandemir
    Compiler-directed application mapping for NoC based chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:155-157 [Conf]
  32. Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu
    Profile-driven energy reduction in network-on-chips. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:394-404 [Conf]

  33. Ring Prediction for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  34. Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach. [Citation Graph (, )][DBLP]


  35. Application mapping for chip multiprocessors. [Citation Graph (, )][DBLP]


  36. Ring data location prediction scheme for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  37. A novel migration-based NUCA design for chip multiprocessors. [Citation Graph (, )][DBLP]


  38. Implementation and evaluation of a migration-based NUCA design for chip multiprocessors. [Citation Graph (, )][DBLP]


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